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LM25118 Arkusz danych(PDF) 6 Page - Texas Instruments |
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LM25118 Arkusz danych(HTML) 6 Page - Texas Instruments |
6 / 43 page LM25118, LM25118-Q1 SNVS726D – JULY 2011 – REVISED AUGUST 2014 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VIN, EN, VOUT to GND –0.3 45 V VCC, LO, VCCX, UVLO to GND –0.3 16 V HB to HS –0.3 16 V HO to HS –0.3 HB+0.3 HS to GND –4 45 CSG, CS to GND –0.3 +0.3 RAMP, SS, COMP, FB, SYNC, RT to GND –0.3 7 Junction Temperature +150 °C (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. 6.2 Handling Ratings MIN MAX UNIT Tstg Storage temperature range –55 150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all 2 V(ESD) Electrostatic discharge kV pins(1)(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) The human body model is a 100 pF capacitor discharged through a 1.5 k Ω resistor into each pin. Applicable standard is JESD-22-A114- C. 6.3 Recommended Operating Conditions (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VIN(2) 3 42 V VCC, VCCX 4.75 14 V Junction Temperature –40 +125 °C (1) Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Operating Range conditions indicate the conditions at which the device is functional and the device should not be operated beyond such conditions. For ensured specifications and conditions, see Electrical Characteristics. (2) VIN ≥ 5.0 V is required to initially start the controller. 6.4 Thermal Information LM25118(Q1) THERMAL METRIC(1) PWP UNIT 20 PINS 110(2) RθJA Junction-to-ambient thermal resistance 40(3) °C/W 35(4) RθJC(bot) Junction-to-case (bottom) thermal resistance 4 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) JEDEC 2-Layer test board (JESD 51-3) (3) JEDEC 4-Layer test board (JESD 51-7) with 4 thermal vias under the Exposed Pad (4) JEDEC 4-Layer test board (JESD 51-7) with 12 thermal vias under the Exposed Pad 6 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: LM25118 LM25118-Q1 |
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