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ML4622 Arkusz danych(PDF) 7 Page - Micro Linear Corporation |
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ML4622 Arkusz danych(HTML) 7 Page - Micro Linear Corporation |
7 / 8 page 7 ML4622, ML4624 critical, the pole it creates can effect the stability of the feedback loop. To avoid stability problems, the value of this capacitor should be at least 10 times larger than the input coupling capacitors. COMPARATOR Two types of comparators are employed in the output section of these Quantizers. The high speed ECL comparator is used to provide the ECL level outputs and in turn drives the TTL comparator. The enable pin, CMP ENABLE, is provided to control the ECL comparator. When CMP ENABLE is low the comparators function normally. When it’s high, it forces ECL+ high, ECL– low, and TTL OUT high. The CMP ENABLE pin can be controlled with TTL level signals when the Quantizer is powered by 5V and ground. LINK DETECT CIRCUIT The Link Detect circuit monitors the input signal and provides a status signal indicating when the input falls below a preset voltage level. When the input falls below the preset voltage level, the TTL Link Mon output changes from active (low) to inactive (high). This signal can be fed to the ML4662 10BASE-FL transceiver or a similar type of function to indicate a Low Light Condition. This output can also be used to disable the output data by tying it to the CMP Enable input. In many fiber optic systems, including Ethernet and Token Ring, a bit error rate is given at a minimum power level. For example, in a 10Base-FL receiver there must be less than 1 x 10–9 bit errors at a receive power level of –32.5dBm average. Designers of these systems must insure that the bit error rate is lower than the specification at the given minimum power level. One procedure to determine the sensitivity of a receiver is to start at the lowest optical power level and gradually increase the optical power until the BER is met. In this case the Link Detect circuit must not disable the receiver (i.e. CMP ENABLE should be tied to Ground). Once the sensitivity of the receiver is determined, the Link Detector circuit can be set just above the power level that meets the BER specification. This way the receiver will shut off before the BER is exceeded. The ML4622 and ML4624 quantizers have greater Link Detect sensitivity, noise immunity, and accuracy than their predecessor the ML4621. The threshold generator shifts the reference voltage at VTHADJ through a circuit which has a temperature coefficient matching that of the limiting amplifier. The relationship between the VTHADJ and the VTH (the peak to peak input threshold) is: VTHADJ = 417 VTH (ML4624) (3) VTHADJ = 500 VTH (ML4622) In most cases, including 10Base-FL, 10Base-FB and Token-Ring, VTHADJ can be tied directly to VREF. However if greater sensitivity is required the circuit in figure 3 can be used to adjust the VTHADJ voltage. Even if VREF is tied to VTHADJ, it is a good idea to layout a board with these two resistors available. This will allow potential future adjustments without board revisions. The response time of the Link Detect circuit is set by the CTIMER pin. Starting from the link off state (i.e., TTL LINK MON is high), the link can be switched on if the input exceeds the set threshold for a time given by: T = CTIMER × 0.7V A 700 µ (4) To switch the link from on to off, the above time will be doubled. Figure 3. VREF VTHADJ THRESH GEN REF R1 R2 (–VRF) BURST MODE In some fiber optic links, the idle signal is DC, or of a frequency that is substantially different from the data. For these links, a faster response time of the DC loop and the Link Monitor is required. The ML4622 and ML4624 has been designed to accommodate these two requirements. The input coupling capacitors can be relatively small and still maintain stability. With smaller input coupling capacitors and VDC capacitor a faster DC loop response time can be achieved. The Link Monitor is also enhanced to have a faster response time. |
Podobny numer części - ML4622 |
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Podobny opis - ML4622 |
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