 |
Zakładka z wyszukiwarką danych komponentów |
|
|
Zakładka z wyszukiwarką danych komponentów |
|
ML4803 Arkusz danych(PDF) 7 Page - Micro Linear Corporation |
|
||||||||||||||||||||||||||||||
ML4803 Arkusz danych(HTML) 7 Page - Micro Linear Corporation |
|
|
7 / 13 page  ML4803 7 February 1999 REF EA – + – + OSC DFF R D Q Q CLK U1 RAMP CLK U4 U3 C1 RL I4 SW2 SW1 + DC I1 I2 I3 VIN L1 VEAO CMP U2 RAMP VEAO TIME VSW1 TIME Figure 3. Typical Leading Edge Control Scheme. current will ramp up. The effective duty cycle of the trailing edge modulation is determined during the ON time of the switch. Figure 2 shows a typical trailing edge control scheme. In the case of leading edge modulation, the switch is turned OFF right at the leading edge of the system clock. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned ON. The effective duty-cycle of the leading edge modulation is determined during the OFF time of the switch. Figure 3 shows a leading edge control scheme. One of the advantages of this control technique is that it requires only one system clock. Switch 1 (SW1) turns OFF and Switch 2 (SW2) turns ON at the same instant to minimize the momentary “no-load” period, thus lowering ripple voltage generated by the switching action. With such synchronized switching, the ripple voltage of the first stage is reduced. Calculation and evaluation have shown that the 120Hz component of the PFC’s output ripple voltage can be reduced by as much as 30% using this method, substantially reducing dissipation in the high- voltage PFC capacitor. TYPICAL APPLICATIONS ONE PIN ERROR AMP The ML4803 utilizes a one pin voltage error amplifier in the PFC section (VEAO). The error amplifier is in reality a current sink which forces 35µA through the output programming resistor. The nominal voltage at the VEAO pin is 5V. The VEAO voltage range is 4 to 6V. For a 11.3M W resistor chain to the boost output voltage and 5V steady state at the VEAO, the boost output voltage would be 400V. PROGRAMMING RESISTOR VALUE Equation 1 calculates the required programming resistor value. Rp VV I VV A M BOOST EAO PGM = − = − = 400 50 35 113 . . µ Ω (1) PFC VOLTAGE LOOP COMPENSATION The voltage-loop bandwidth must be set to less than 120Hz to limit the amount of line current harmonic distortion. A typical crossover frequency is 30Hz. Equation 1, for simplicity, assumes that the pole capacitor dominates the error amplifier gain at the loop unity-gain frequency. Equation 2 places a pole at the crossover frequency, providing 45 degrees of phase margin. Equation 3 places a zero one decade prior to the pole. Bode plots showing the overall gain and phase are shown in Figures 5 and 6. Figure 4 displays a simplified model of the voltage loop. C Pin RV VEAO C f COMP p BOOST OUT = ×× × × × × ∆ 2 2 π 16 (2) C W MV V F Hz COMP = ´´ ´ ´ ´ ´ 300 113 400 0 5 220 2 30 2 .. Wm p 05 CnF COMP = 16 LEADING/TRAILING MODULATION (Continued) |
Podobny numer części - ML4803 |
|
Podobny opis - ML4803 |
|
|
|
Link URL |
| Polityka prywatności |
| ALLDATASHEET.PL |
| Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Polish ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
