InGaAs linear image sensors

G11135-256DD, G11135-512DE

8

Terminal name

Input/Output

Function and recommended connection

Remark

PDN

Input

Cathode bias terminal for InGaAs photodiode

4.0 V

AD_sp

Output

Digital start signal for A/D conversion

0 to 5 V

Cf_select

Signal for selecting feedback capacitance (integration capacitance) on CMOS chip

0 V or 5 V

Thermistor

Output

Thermistor for monitoring temparature inside the package

-

AD_trig

Output

Sampling synchronous signal for A/D conversion

0 to 5 V

RESET

Input

Reset pulse for initializing the feedback capacitance in the charge amplifier

formed in the CMOS chip. Integration time is determined by the high period of

this pulse.

0 to 5 V

CLK

Input

Clock pulse for operating the CMOS shift register

0 to 5 V

INP

Input

Input stage amplifier reference voltage. Supply voltage for operating the signal

processing circuit in the CMOS chip.

4.0 V

Vinp

Input

Video line reset voltage. Supply voltage for operating the signal processing

circuit in the CMOS chip.

4.0 V

Fvref

Input

Differential amplifier reference voltage. Supply voltage for operating the signal

processing circuit in the CMOS chip.

1.2 V

VIDEO

Output

Differential amplifier output. Analog video signal.

1.25 to 3.85 V

Vdd

Input

Supply voltage for operating the signal processing circuit in the CMOS chip (+5 V)

5 V

GND

Input

Grand for the signal processing circuit in the CMOS chip (0 V)

0 V

*

9: Conversion efficiency is determined by supply voltage to the Cf_select terminals as shown below.

Pin connections

Conversion efficiency

Cf_select

High

Low

Low: 0 V (GND), High: 5 V (Vdd)