LC78615E

www.onsemi.com

2

Detail of Functions

[CD-DSP functions]

< Playback functions>

 Playback mode : CLV playback / Jitter free playback (VCEC)

 Playback speed : Normal speed, double speed, quadruple speed (CLV playback / Jitter free playback)

<RF processing block>

 RF system : AGC, CD-R and CD-R/W playback support, peak hold, bottom hold

 Error system : TE signal generation, FE signal generation

 Detection : Track count signal, Jitter, Defect (black, mirror)

 LASER power controller (APC)

 DC offset voltage cancellation

<Servo control block>

 All servo systems as tracking, focus, sled and spindle are implemented with digital processing.

 Automatic adjustment functions : focus gain, focus bias, focus offset,

tracking gain, tracking offset and tracking balance

 Shock detection / Interruption detection

<CD signal processing block>

 EFM signal synchronization detection, protection and interpolation

 Error detection, correction (C1=double, C2=quadruple/double)

 Jitter margin ±19 frames

<CD-TEXT processing block>

 Buffers CD-TEXT decoded data to the buffer memory.

 Starts buffering of CD-TEXT decoded data from desired ID3/ID4.

[CD data processing functions]

<CDDA data processing block>

 Interpolation

 Mute function(

12dB, ∞)

 Digital attenuator

 De-emphasis filter

<CDROM data processing block >

 CLV playback

: Fixed normal speed or double speed

 Jitter free playback (VCEC) : Free speed within quadruple speed

<Outputs format >

 Digital 3 lines output (LRCK, BCK, DATA)

 Supports various external audio data output format

IIS (48fs), MSB First, Right-Justified, Left-Justified (32fs/48fs), 16 bit data length

 Slave mode

Output DATA synchronized to external Clock input (LRCK/BCK)

 Digital output (S/PDIF, only CLV playback mode)

[Internal Microcontroller functions]

<Sequencer control>

 CD playback control

Servo control, CD-TEXT processing, Digital data output control, etc.

<Communication control between main controller>

 The SIO interface using CE,CL,DI,DO and BUSYB pins is available as communication format.

 External main controller can control this IC directly such as “stop oscillation” or “restart oscillation” or so

on at the internal register open mode (REG_READY high condition).

 Even while the clock is stopped, some of general port can be controlled by host controller.

<Peripheral interface block>

 GPIO port

15 ports maximum(Shared with other functionslerate.)

<Program memory block>

 Mask-ROM type

 ROM Collect function is built in for the partial change of the program and Host controller can use this.

<Others>

 Watch Dog Timer

Notifies to outside from a pin or resets internally.

 Power management (Two kinds of sleep mode)

(1) Only the clock for CPU core is operating and clocks for other blocks are stopping.

(2) All clocks are stopping.

[Others]

<Internal power supply>

 1.5V regulator for internal blocks