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ACE9050 Arkusz danych(PDF) 3 Page - Mitel Networks Corporation |
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ACE9050 Arkusz danych(HTML) 3 Page - Mitel Networks Corporation |
3 / 52 page ACE9050 3 FUNCTIONAL OVERVIEW MICROPROCESSOR UNIT The processor unit is program compatible with the standard 6303R. It contains the following hardware: 8-bit CPU Serial Communication Interface: SCI (UART) 16-bit timer/counter 8-bit l/O port (P1) 2-bit l/O port (P2) The processor bus speed can be either 1·008 MHz or 2·016 MHz. An Emulation mode is provided whereby the internal 6303 is bypassed to allow software development on a standard 6303 In-Circuit Emulator (ICE). MEMORY The ACE9050 contains 512 bytes ofROM and 6144 bytes of RAM internally. The ROM code facilitates system initiation after a reset and the programming of FLASH memory via the 6303 SCI (UART). The Internal RAM area represents the total RAM requirement anticipated for a cellular phone. BUS INTERFACE and MEMORY BANK SWITCHING These blocks create the Data, Address and Control lines for the external memory. The external address bus is expanded from the standard 16 bits up to 18 bits by a banked addressing scheme. This increases the memory address space from 64K to 256K. Two programmable Chip Selects (CSEPN and CSE2N) are generated. The Memory Interface will operate down to 13V, allowing the use of low voltage memory parts. In Emulation mode the external processor controls the ACE9050 via the Bus Interface block. EXTERNAL PORTS The ACE9050 contains two Keypad Interface ports, two maskable external interrupts, and both Input and Output ports. These are in addition to the 6303 bidirectional Port1 and Port2. The Output port provides two high current outputs for driving LEDs. DECODER and INTERRUPT CONTROL The Decoder block memory maps ACE9050 register locations onto the processor’s address space. The Interrupt Control block handles both internal and external interrupt sources. These are fed into control logic allowing individual masking and reset by software. The Interrupt control logic output is internally connected to the 6303 IRQ and also drives an external pin. ACE SERIAL INTERFACE (SINT) and I2C Three serial interface protocols are supported: UART, I2C and ACEBus. The 6303 provides a UART interface via the SCI block. The ACE9050 I2C block provides an I2C interface with both Master and Slave capability. The ACEBus is designed for use with the ACE Chipset and has a data rate of just over 1MBits/sec. Three Latch pulse are available to target data at the relevant IC and control the ACE9030 Synthesiser. BEEP, ALARM and RING TONE GENERATOR (BAR) The BAR Generator is intended to drive an acoustic tone transducer. It has a programmable single digital pulse train output. MODEM and SAT MANAGEMENT The Modem provides two way data transfer and SAT management over the radio link between a base station and phone handset. AMPS and TACS data rates are supported . The Modem block contains: Digital Discriminator, Data Decoder and Word Synchronising hardware. Various modes can be selected by software. A squelch level is also set by software so that the quality of each data byte can be assessed. SAT detection and generation at the standard three frequencies 5970Hz, 6000Hz and 6030Hz is included. WATCHDOG and POWER CONTROL (ATO) The Watchdog function will provide an internal and external Reset if the processor does not make a write access to a defined address every 4 seconds. An Autonomous Time Out circuit (ATO) will drive the POFFN output low if Transmitter power is detected without Receiver power, independent of any processor operation. POFFN must be used in conjunction with external regulators to control power to the mobile handset. IF CONTROL COUNTER (IFC) The Intermediate Frequency Control (IFC) Counter is used as part of an AFC Loop. The IFC Counter provides a pulse after a set number of IF input pulses. The IFC Counter output is connected to the 6303 timer input and an external pin (ICN). TWIN PULSE WIDTH MODULATORS Two independently programmable Pulse Width Modulators (PWMs) are available. These provide digital output pulse trains, controllable by software. The output can be filtered externally to provide a DAC function. Typical applications are battery charging control and LCD contrast control. CLOCK GENERATOR The Clock Generator provides all the various internal and external clocks from a single 8·064 MHz source. The source can either be an external crystal or the ACE9030. |
Podobny numer części - ACE9050 |
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Podobny opis - ACE9050 |
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