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TMP101-Q1 Arkusz danych(PDF) 9 Page - Texas Instruments

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Numer części TMP101-Q1
Szczegółowy opis  DIGITAL TEMPERATURE SENSOR WITH I2C INTERFACE
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Producent  TI [Texas Instruments]
Strona internetowa  http://www.ti.com
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TMP100-Q1
TMP101-Q1
www.ti.com
SBOS581
– SEPTEMBER 2011
Table 8. Resolution of the TMP100-Q1 and TMP101-Q1
CONVERSION TIME
R1
R0
RESOLUTION
(typical)
0
0
9 Bits (0.5
°C)
40 ms
0
1
10 Bits (0.25
°C)
80 ms
1
0
11 Bits (0.125
°C)
160 ms
1
1
12 Bits (0.0625
°C)
320 ms
OS/ALERT (OS)
The TMP100-Q1 and TMP101-Q1 feature a One-Shot Temperature Measurement Mode. When the device is in
Shutdown Mode, writing a 1 to the OS/ALERT bit will start a single temperature conversion. The device will
return to the shutdown state at the completion of the single conversion. This is useful to reduce power
consumption in the TMP100-Q1 and TMP101-Q1 when continuous monitoring of temperature is not required.
Reading the OS/ALERT bit will provide information about the Comparator Mode status. The state of the POL bit
will invert the polarity of data returned from the OS/ALERT bit. For POL = 0, the OS/ALERT will read as 1 until
the temperature equals or exceeds THIGH for the programmed number of consecutive faults, causing the
OS/ALERT bit to read as 0. The OS/ALERT bit will continue to read as 0 until the temperature falls below TLOW
for the programmed number of consecutive faults when it will again read as 1. The status of the TM bit does not
affect the status of the OS/ALERT bit.
HIGH AND LOW LIMIT REGISTERS
In Comparator Mode (TM = 0), the ALERT pin of the TMP101-Q1 becomes active when the temperature equals
or exceeds the value in THIGH and generates a consecutive number of faults according to fault bits F1 and F0.
The ALERT pin will remain active until the temperature falls below the indicated TLOW value for the same number
of faults.
In Interrupt Mode (TM = 1) the ALERT Pin becomes active when the temperature equals or exceeds THIGH for a
consecutive number of fault conditions. The ALERT pin remains active until a read operation of any register
occurs or the device successfully responds to the SMBus Alert Response Address. The ALERT pin will also be
cleared if the device is placed in Shutdown Mode. Once the ALERT pin is cleared, it will only become active
again by the temperature falling below TLOW. When the temperature falls below TLOW, the ALERT pin will become
active and remain active until cleared by a read operation of any register or a successful response to the SMBus
Alert Response Address. Once the ALERT pin is cleared, the above cycle will repeat with the ALERT pin
becoming active when the temperature equals or exceeds THIGH. The ALERT pin can also be cleared by
resetting the device with the General Call Reset command. This will also clear the state of the internal registers
in the device returning the device to Comparator Mode (TM = 0).
Both operational modes are represented in . Table 9 and Table 10 describe the format for the THIGH and TLOW
registers. Power-up Reset values for THIGH and TLOW are: THIGH = 80°C and TLOW = 75°C. The format of the data
for THIGH and TLOW is the same as for the Temperature Register.
Table 9. Bytes 1 and 2 of THIGH Register
BYTE
D7
D6
D5
D4
D3
D2
D1
D0
1
H11
H10
H9
H8
H7
H6
H5
H4
BYTE
D7
D6
D5
D4
D3
D2
D1
D0
2
H3
H2
H1
H0
0
0
0
0
Table 10. Bytes 1 and 2 of TLOW Register
BYTE
D7
D6
D5
D4
D3
D2
D1
D0
1
L11
L10
L9
L8
L7
L6
L5
L4
BYTE
D7
D6
D5
D4
D3
D2
D1
D0
2
L3
L2
L1
L0
0
0
0
0
Copyright
© 2011, Texas Instruments Incorporated
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