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I2041AF-08SR Arkusz danych(PDF) 2 Page - ON Semiconductor |
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I2041AF-08SR Arkusz danych(HTML) 2 Page - ON Semiconductor |
2 / 7 page P2041A http://onsemi.com 2 Figure 1. Block Diagram ModOUT PLL VCO Output Divider VDD VSS Loop Filter Phase Detector Modulation SR0 SR1 SSON Crystal Oscillator Frequency Divider Feedback Divider XOUT XIN Table 1. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Rating Unit VDD, VIN Voltage on any pin with respect to Ground −0.5 to +7.0 V TSTG Storage temperature −65 to +125 °C TA Operating temperature −40 to +85 °C Ts Max. Soldering Temperature (10 sec) 260 °C TJ Junction Temperature 150 °C TDV Static Discharge Voltage (As per JEDEC STD22− A114−B) 2 KV Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 2. PIN DESCRIPTION Pin# Pin Name Type Description 1 XIN / CLK I Connect to crystal or externally generated clock signal. 2 XOUT I Connect to crystal. No connect if externally generated clock signal is used. 3 SR1 I Digital logic input used to select Spreading Range (see Table 3). This pin has an internal pull−up resistor. 4 VSS P Ground Connection. Connect to system ground. 5 SSON I Digital logic input used to enable Spread Spectrum function (Active Low). Spread Spectrum function enable when low. This pin has an internal pull−low resistor. 6 ModOUT O Spread Spectrum Clock Output. 7 SR0 I Digital logic input used to select Spreading Range (see Table 3). This pin has an internal pull−up resistor. 8 VDD P Connect to +3.3 V or +5.0 V. |
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