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EZR32WG230F128R55G Arkusz danych(PDF) 4 Page - Silicon Laboratories |
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EZR32WG230F128R55G Arkusz danych(HTML) 4 Page - Silicon Laboratories |
4 / 87 page 3. System Overview 3.1 Introduction The EZR32WG230 Wireless MCUs are the latest in Silicon Labs family of wireless MCUs delivering a high performance, low energy wireless solution integrated into a small form factor package. By combining a high performance sub-GHz RF transceiver with an energy efficient 32-bit ARM Cortex-M4, the EZR32WG family provides designers with the ultimate in flexibility with a family of pin-compatible parts that scale from 64 to 256 kB of flash and support Silicon Labs EZRadio or EZRadioPRO transceivers. The ultra-low power operat- ing modes and fast wake-up times combined with the low transmit and receive power consumption of the sub-GHz radio result in a solution optimized for low power and battery powered applications. For a complete feature set and in-depth information on the modules, the reader is referred to the EZR32WG Reference Manual. The EZR32WG230 block diagram is shown below. Figure 3.1. Block Diagram 3.1.1 ARM Cortex-M4 Core The ARM Cortex-M4 includes a 32-bit RISC processor which can achieve as much as 1.25 Dhrystone MIPS/MHz. A Memory Protection Unit with support for up to 8 memory segments is included, as well as a Wake-up Interrupt Controller handling interrupts triggered while the CPU is asleep. The EZR32 implementation of the Cortex-M4 is described in detail in EZR32 Cortex-M4 Reference Manual. 3.1.2 Debugging These devices include hardware debug support through a 2-pin serial-wire debug interface and an Embedded Trace Module (ETM) for data/instruction tracing. In addition there is also a 1-wire Serial Wire Viewer pin which can be used to output profiling information, data trace and software-generated messages. 3.1.3 Memory System Controller (MSC) The Memory System Controller (MSC) is the program memory unit of the EZR32WG microcontroller. The flash memory is readable and writable from both the Cortex-M4 and DMA. The flash memory is divided into two blocks: the main block and the information block. Program code is normally written to the main block. Additionally, the information block is available for special user data and flash lock bits. There is also a read-only page in the information block containing system and device calibration data. Read and write operations are supported in the energy modes EM0 and EM1. EZR32WG230 Data Sheet System Overview silabs.com | Smart. Connected. Energy-friendly. Rev. 1.1 | 3 |
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