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AD7124-4BCPZ Arkusz danych(PDF) 11 Page - Analog Devices

Numer części AD7124-4BCPZ
Szczegółowy opis  4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD7124-4BCPZ Arkusz danych(HTML) 11 Page - Analog Devices

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Data Sheet
AD7124-4
Rev. A | Page 11 of 90
Parameter1, 2
Min
Typ
Max
Unit
Test Conditions/Comments
WRITE OPERATION
t8
0
ns
CS falling edge to SCLK active edge5 setup time
t9
30
ns
Data valid to SCLK edge setup time
t10
25
ns
Data valid to SCLK edge hold time
t11
0
ns
CS rising edge to SCLK edge hold time
1
These specifications were sample tested during the initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of IOVDD and
timed from a voltage level of IOVDD/2.
2
See Figure 3, Figure 4, Figure 5, and Figure 6.
3
MCLK is the master clock frequency.
4
These specifications are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
5
The SCLK active edge is the falling edge of SCLK.
6
These specifications are derived from the measured time taken by the data output to change by 0.5 V when loaded with the circuit shown in Figure 2. The measured
number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. The times quoted in the timing characteristics are the true bus
relinquish times of the device and, therefore, are independent of external bus loading capacitances.
7
RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high,
although subsequent reads must not occur close to the next output update. In continuous read mode, the digital word can be read only once.
8
When the CS_EN bit is cleared, the DOUT/RDY pin changes from its DOUT function to its RDY function, following the last inactive edge of the SCLK. When CS_EN is set,
the DOUT pin continues to output the LSB of the data until the CS inactive edge.
Timing Diagrams
Figure 2. Load Circuit for Timing Characterization
Figure 3. Read Cycle Timing Diagram (CS_EN Bit Cleared)
IOVDD/2
TO OUTPUT PIN
ISOURCE (100µA)
ISINK (100µA)
25pF
t3
t2
t7
t6
t5
t4
t1
MSB
LSB
DOUT/RDY (O)
SCLK (I)
CS (I)
I = INPUT, O = OUTPUT


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