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AD9154BCPZRL Arkusz danych(PDF) 9 Page - Analog Devices |
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AD9154BCPZRL Arkusz danych(HTML) 9 Page - Analog Devices |
9 / 124 page Data Sheet AD9154 Rev. B | Page 9 of 124 LATENCY VARIATION SPECIFICATIONS AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V, TA = 25°C, IOUTFS = 20 mA, unless otherwise noted. Table 7. Parameter Test Conditions/Comments Min Typ Max Unit DAC LATENCY VARIATION Subclass 1 PLL Off 0 1 DACCLK cycles PLL On −1 +1 DACCLK cycles JESD204B INTERFACE ELECTRICAL SPECIFICATIONS AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V, TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted. Table 8. Parameter Symbol Test Conditions/Comments Min Typ Max Unit JESD204B DATA INPUTS Input Leakage Current T A = 25°C Logic High Input level = 1.2 V ± 0.25 V, V TT = 1.2 V 10 µA Logic Low Input level = 0 V −4 µA Unit Interval UI 94 714 ps Common-Mode Voltage V RCM AC-coupled −0.05 +1.85 V V TT = SVDD12 1 Differential Voltage R_V DIFF 110 1050 mV V TT Source Impedance Z TT At dc 30 Ω Differential Impedance Z RDIFF At dc 80 100 120 Ω Differential Return Loss RL RDIF 8 dB Common-Mode Return Loss RL RCM 6 dB DIFFERENTIAL OUTPUTS (SYNCOUT±)2 Output Offset Voltage V OS 1.19 1.27 V DETERMINISTIC LATENCY Fixed 17 PClock3 cycles Variable 2 PClock3 cycles SYSREF± TO LOCAL MULTIFRAME CLOCK (LMFC) DELAY 4 DAC clock cycles 1 As measured on the input side of the ac coupling capacitor. 2 IEEE Standard 1596.3 LVDS compatible. 3 PClock is the AD9154 internal processing clock; its frequency is equal to the JESD204B lane rate ÷ 40. |
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