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LM15851NKET Arkusz danych(PDF) 9 Page - Texas Instruments

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Numer części LM15851NKET
Szczegółowy opis  Ultra-Wideband RF Sampling Subsystem
Download  87 Pages
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Producent  TI1 [Texas Instruments]
Strona internetowa  http://www.ti.com
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LM15851NKET Arkusz danych(HTML) 9 Page - Texas Instruments

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LM15851
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SLAS990D – JANUARY 2014 – REVISED JULY 2015
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all
±500
pins(2)
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
All voltages are measured with respect to GND = 0 V, unless otherwise specified.
MIN
MAX
UNIT
1.2-V supply: VA12, VD12
1.14
1.26
V
VDD
Supply voltage
1.9-V supply: VA19
1.8
2
V
1.9 supply
≥ 1.2
Supply sequence (power-up and power-down)
V
supply
VCMI
Analog input common mode voltage
V(VCMO) – 0.15
V(VCMO) + 0.15
V
VIN+, VIN– voltage (maintaining common mode)
0
V(VA19)
V
DEVCLK±, SYSREF±, ~SYNC± pin voltage range
0
V(VA19)
V
VID(CLK)
Differential DEVCLK±, SYSREF±, ~SYNC± amplitude
0.4
2
VPP
VCM(CLK)
SYSREF±, ~SYNC± Common Mode
0.64
1.1
V
TA
Ambient temperature
–40
85
°C
TJ
Junction temperature
135
°C
6.4 Thermal Information
LM15851
THERMAL METRIC(1)
NKE (VQFN)
UNIT
68 PINS
RθJA
Thermal resistance, junction-to-ambient
19.8
°C/W
RθJCbot
Thermal resistance, junction-to-case (bottom)
2.7
°C/W
ψJB
Characterization parameter, junction-to-board
9.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN full scale range at default
setting (725 mVPP), VIN = –1 dBFS, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 4 GHz at 0.5 VPP with 50% duty
cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a foreground (FG) mode calibration with timing calibration enabled. Typical values are at
TA = 25°C.
(1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE CHARACTERISTICS
Third-order intermodulation
F1 = 2110 MHz at
−13 dBFS
IMD3
–64
dBc
distortion
F2 = 2170 MHz at
−13 dBFS
DECIMATE-BY-4 MODE
TA = 25°C
59.9
Signal-to-noise ratio,
TA = TMIN to TMAX
56.2
FIN = 600 MHz, –1 dBFS, decimate-by-4
integrated across DDC alias
mode
SNR1
protected output bandwidth
TA = 25°C, calibration = BG
59.2
dBFS
Input frequency-dependent
TA = TMIN to TMAX, calibration = BG
53.3
interleaving spurs included
FIN = 2400 MHz, –1 dBFS, decimate-by-4 mode
56.4
(1)
To ensure accuracy, the VA19, VA12, and VD12 pins are required to be well bypassed. Each supply pin must be decoupled with one or
more bypass capacitors.
(2)
Interleave related fixed frequency spurs at ƒS / 4 and ƒS / 2 are excluded from all SNR, SINAD, ENOB and SFDR specifications. The
magnitude of these spurs is provided separately.
Copyright © 2014–2015, Texas Instruments Incorporated
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