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54ACTQ841F Arkusz danych(PDF) 2 Page - National Semiconductor (TI) |
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54ACTQ841F Arkusz danych(HTML) 2 Page - National Semiconductor (TI) |
2 / 8 page Connection Diagrams Functional Description The ’ACTQ841 consists of ten D-type latches with TRI-STATE outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. This allows asynchro- nous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup and hold time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. Function Table Inputs Internal Output Function OE LE D Q O X X X X Z High Z H H L L Z High Z H H H H Z High Z H L X NC Z Latched L H L L L Transparent L H H H H Transparent L L X NC NC Latched H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impendance NC = No Change Logic Diagram Pin Assignment for DIP and Flatpack DS100250-3 Pin Assignment for LCC DS100250-4 DS100250-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 |
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