OBSOLETE

LM2466

SNOSA14B – SEPTEMBER 2003 – REVISED APRIL 2013

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THEORY OF OPERATION

The LM2466 is a high voltage monolithic three channel CRT driver suitable for high resolution display

applications. The LM2466 operates with 80V and 12V power supplies. The part is housed in the industry

standard 9-lead TO-220 molded plastic power package.

The circuit diagram of the LM2466 is shown in Figure 1. The PNP emitter follower, Q5, provides input buffering.

Q1 and Q2 form a fixed gain cascode amplifier with resistors R1 and R2 setting the gain at

−20. Emitter followers

Q3 and Q4 isolate the high output impedance of the cascode stage from the capacitance of the CRT cathode

which decreases the sensitivity of the device to load capacitance. Q6 provides biasing to the output emitter

follower stage to reduce crossover distortion at low signal levels.

Figure 2 shows a typical test circuit for evaluation of the LM2466. This circuit is designed to allow testing of the

LM2466 in a 50

Ω environment without the use of an expensive FET probe. In this test circuit, the two 2.49kΩ

resistors form a 200:1 wideband, low capacitance probe when connected to a 50

Ω coaxial cable and a 50Ω load

(such as a 50

Ω oscilloscope input). The input signal from the generator is ac coupled to the base of Q5.

APPLICATION HINTS

Introduction

Texas Instruments (TI) is committed to provide application information that assists our customers in obtaining the

best performance possible from our products. The following information is provided in order to support this

commitment. The reader should be aware that the optimization of performance was done using a specific printed

circuit board designed at TI. Variations in performance can be realized due to physical changes in the printed

circuit board and the application. Therefore, the designer should know that component value changes may be

required in order to optimize performance in a given application. The values shown in this document can be used

as a starting point for evaluation purposes. When working with high bandwidth circuits, good layout practices are

also critical to achieving maximum performance.

Important Information

The LM2466 performance is targeted for the VGA (640 x 480) to XGA (1024 x 768, 85 Hz refresh) resolution

market. The application circuits shown in this document to optimize performance and to protect against damage

from CRT arcover are designed specifically for the LM2466. If another member of the LM246X family is used,

please refer to its datasheet.

Power Supply Bypass

Since the LM2466 is a wide bandwidth amplifier, proper power supply bypassing is critical for optimum

performance. Improper power supply bypassing can result in large overshoot, ringing or oscillation. 0.1 µF

practical. Additionally, a 47 µF or larger electrolytic capacitor should be connected from both supply pins to

ground reasonably close to the LM2466.

Arc Protection

During normal CRT operation, internal arcing may occasionally occur. Spark gaps, in the range of 200V,

connected from the CRT cathodes to CRT ground will limit the maximum voltage, but to a value that is much

higher than allowable on the LM2466. This fast, high voltage, high energy pulse can damage the LM2466 output

stage. The application circuit shown in Figure 9 is designed to help clamp the voltage at the output of the

LM2466 to a safe level. The clamp diodes, D1 and D2, should have a fast transient response, high peak current

rating, low series impedance and low shunt capacitance. FDH400 or equivalent diodes are recommended. Do

and ground respectively. The cathode of D1 should be located very close to a separately decoupled bypass

capacitor (C3 in Figure 9). The ground connection of D2 and the decoupling capacitor should be very close to the

LM2466 ground. This will significantly reduce the high frequency voltage transients that the LM2466 would be

subjected to during an arcover condition. Resistor R2 limits the arcover current that is seen by the diodes while

R1 limits the current into the LM2466 as well as the voltage stress at the outputs of the device. R2 should be a

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