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LM25066PSQ Arkusz danych(PDF) 8 Page - Texas Instruments |
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LM25066PSQ Arkusz danych(HTML) 8 Page - Texas Instruments |
8 / 63 page LM25066 SNVS654J – FEBRUARY 2010 – REVISED DECEMBER 2015 www.ti.com Electrical Characteristics (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of –40°C to 85°C unless otherwise stated. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 12 V (see (1) and (2)). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN = 12 V, VIN – SENSE = 25 mV, PINACC Input power accuracy –3% 3% CL = GND REMOTE DIODE TEMPERATURE SENSOR Temperature accuracy using local diode TA = 10°C to 85°C 2 10 °C TACC Remote diode resolution 9 bits High level 250 300 µA IDIODE External diode current source Low level 9.4 µA Diode current ratio 26 PMBUS PIN THRESHOLDS (SMBA, SDA, SCL) VIL Data, clock input low voltage 0.8 V VIH Data, clock input high voltage 2.1 5.5 V VOL Data output low voltage IPULLUP = 500 µA 0 0.4 V ILEAK Input leakage current SDA, SMBA, SCL = 5 V 1 µA CONFIGURATION PIN THRESHOLDS (CB, CL, RETRY) VIH Threshold voltage 3 V ILEAK Input leakage current CL, CB, RETRY = 5 V 1 mA 7.6 Timing Requirements MIN NOM MAX UNIT FSMB SMBus operating frequency 10 400 kHz tBUF Bus free time between stop and start condition 1.3 µs Hold time after (repeated) start condition. After this period, the first clock is tHD:STA 0.6 µs generated. tSU:STA Repeated start condition setup time 0.6 µs tSU:STO Stop condition setup time 0.6 µs tHD:DAT Data hold time 300 ns tSU:DAT Data setup time 100 ns tTIMEOUT Clock low time-out(1) 25 35 ms tLOW Clock low period 1.5 µs tHIGH Clock high period(2) 0.6 µs tLOW:SEXT Cumulative clock low extend time (slave device)(3) 25 ms tLOW:MEXT Cumulative low extend time (master device)(4) 10 ms tF Clock or data fall time(5) 20 300 ns tR Clock or data rise time(5) 20 300 ns (1) Devices participating in a transfer will timeout when any clock low exceeds the value of TTIMEOUT,MIN of 25 ms. Devices that have detected a timeout condition must reset the communication no later than TTIMEOUT,MAX of 35 ms. The maximum value must be adhered to by both a master and a slave as it incorporates the cumulative stretch limit for both a master (10 ms) and a slave (25 ms). (2) THIGH MAX provides a simple method for devices to detect bus idle conditions. (3) TLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to the stop. If a slave exceeds this time, it is expected to release both its clock and data lines and reset itself. (4) TLOW:MEXT is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from start-to-ack, ack-to-ack, or ack-to-stop. (5) Rise and fall time are defined with TR = ( VILMAX – 0.15) to (VIHMIN + 0.15) and TF = 0.9 VDD to (VILMAX – 0.15). 8 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LM25066 |
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