Data Sheet

AD7091R-5

Rev. 0 | Page 5 of 34

Table 2.

Parameter

Min

Typ

Max

Unit

Description

100

kHz

Serial clock frequency, standard mode

400

kHz

Fast mode

4

µs

SCL high time, standard mode

0.6

µs

Fast mode

4.7

µs

SCL low time, standard mode

1.3

µs

Fast mode

250

ns

Data setup time, standard mode

100

ns

Fast mode

0

3.45

µs

Data hold time, standard mode

0

0.9

µs

Fast mode

4.7

µs

Setup time for a repeated start condition, standard mode

0.6

µs

Fast mode

4

µs

Hold time for a repeated start condition, standard mode

0.6

µs

Fast mode

4.7

µs

Bus-free time between a stop and a start condition, standard mode

1.3

µs

Fast mode

4

µs

Setup time for a stop condition, standard mode

0.6

µs

Fast mode

1000

ns

Rise time of the SDA signal, standard mode

300

ns

Fast mode

300

ns

Fall time of the SDA signal, standard mode

300

ns

Fast mode

1000

ns

Rise time of the SCL signal, standard mode

300

ns

Fast mode

1000

ns

Rise time of the SCL signal after a repeated; not shown in Figure 2, standard mode

300

ns

Start condition and after an acknowledge bit, fast mode

300

ns

Fall time of the SCL signal, standard mode

300

ns

Fast mode

0

50

ns

Pulse width of the suppressed spike; not shown in Figure 2, fast mode

10

ns

RESET pulse width (see Figure 35)

50

ns

RESET pulse delay upon power-up (see Figure 35)

1

A device must provide a data hold time for SDA to bridge the undefined region of the SCL falling edge.

SCL

S

SDA

S = START CONDITION

P = STOP CONDITION

P

P

S

Figure 2. 2-Wire Serial Interface Timing Diagram