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AD7172-4BCPZ-RL Arkusz danych(PDF) 6 Page - Analog Devices |
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AD7172-4BCPZ-RL Arkusz danych(HTML) 6 Page - Analog Devices |
6 / 61 page AD7172-4 Data Sheet Rev. A | Page 6 of 61 Parameter Test Conditions/Comments Min Typ Max Unit POWER SUPPLY CURRENTS All outputs unloaded, digital inputs connected to IOVDD or DGND Full Operating Mode AVDD1 Current AVDD1 = 5 V Typical, 5.5 V Maximum AIN± and REF± buffers disabled 0.23 0.29 mA AIN± and REF± buffers enabled 1.7 2.15 mA Each buffer: AIN± and REF± 0.38 mA AVDD1 = 3.3 V Typical, 3.6 V Maximum1 AIN± and REF± buffers disabled 0.15 0.2 mA AIN± and REF± buffers enabled 1.45 1.9 mA Each buffer: AIN± and REF± 0.33 mA AVDD2 Current 1 1.1 mA IOVDD Current External clock 0.33 0.5 mA Internal clock 0.61 0.82 mA External crystal 0.98 mA Standby Mode LDO on 32 µA Power-Down Mode Full power-down including LDO 1 10 µA POWER DISSIPATION Full Operating Mode Unbuffered, external clock; AVDD1 = 3.3 V, AVDD2 = 2 V, IOVDD = 2 V 3.16 mW Unbuffered, external clock; all supplies = 5 V 7.8 mW Unbuffered, external clock; all supplies = 5.5 V 10.4 mW Fully buffered, internal clock; AVDD1 = 3.3 V, AVDD2 = 2 V, IOVDD = 2 V 8 mW Fully buffered, internal clock; all supplies = 5 V 16.6 mW Fully buffered, internal clock; all supplies = 5.5 V 22.4 mW Standby Mode All supplies = 5 V 160 µW Power-Down Mode Full power-down, all supplies = 5 V 5 µW Full power-down, all supplies = 5.5 V 55 µW 1 Specification is not production tested but is supported by characterization data at initial product release. 2 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale calibration reduces the gain error to the order of the noise for the programmed output data rate. |
Podobny numer części - AD7172-4BCPZ-RL |
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Podobny opis - AD7172-4BCPZ-RL |
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