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AD5346BCP-REEL Arkusz danych(PDF) 7 Page - Analog Devices |
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AD5346BCP-REEL Arkusz danych(HTML) 7 Page - Analog Devices |
7 / 24 page AD5346/AD5347/AD5348 Rev. 0 | Page 7 of 24 AD5346 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TOP VIEW (Not to Scale) 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 AD5346 LDAC A1 A0 WR CS AGND VOUTD VREFCD VREFEF VREFGH VOUTC VOUTB VOUTA VREFAB PD VDD DB0 DB1 DB2 CLR GAIN DB7 DB6 DB3 DB4 DB5 8-BIT VOUTH VOUTG VOUTF VOUTE DGND A2 RD BUF DGND DGND DGND DGND Figure 5. AD5346 Pin Configuration—TSSOP 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 40 39 38 37 36 35 34 33 32 31 CS AGND VOUTD VOUTC VOUTB VOUTA DB0 DB1 DB2 DB7 DB6 DB3 DB4 DB5 VOUTH VOUTG VOUTF VOUTE RD AGND TOP VIEW (Not to Scale) AD5346 8-BIT Figure 6. AD5346 Pin Configuration—LFCSP Table 5. AD5346 Pin Function Descriptions Pin Number TSSOP LFCSP Mnemonic Function 1 35 VREFGH Reference Input for DACs G and H. 2 36 VREFEF Reference Input for DACs E and F. 3 37 VREFCD Reference Input for DACs C and D. 4 38, 39 VDD Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Both VDD pins on the LFCSP package must be at the same potential. 5 40 VREFAB Reference Input for DACs A and B. 6–9, 11–14 1–4, 7–10 VOUTX Output of DAC X. Buffered output with rail-to-rail operation. 10 5, 6 AGND Analog Ground. Ground reference for analog circuitry. 15, 21–24 11, 17–20 DGND Digital Ground. Ground reference for digital circuitry. 16 12 BUF Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered. 17 13 LDAC Active Low Control Input. Updates the DAC registers with the contents of the input registers, which allows all DAC outputs to be simultaneously updated. 18 14 A0 LSB Address Pin. Selects which DAC is to be written to. 19 15 A1 Address Pin. Selects which DAC is to be written to. 20 16 A2 MSB Address Pin. Selects which DAC is to be written to. 25–32 21–28 DB0–DB7 Eight Parallel Data Inputs. DB7 is the MSB of these eight bits. 33 29 CS Active Low Chip Select Input. Used in conjunction with WR to write data to the parallel interface, or with RD to read back data from a DAC. 34 30 RD Active Low Read Input. Used in conjunction with CS to read data back from the internal DACs. 35 31 WR Active Low Write Input. Used in conjunction with CS to write data to the parallel interface. 36 32 GAIN Gain Control Pin. Controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF. 37 33 CLR Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros. 38 34 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode. |
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