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LF298M Arkusz danych(PDF) 6 Page - Texas Instruments |
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LF298M Arkusz danych(HTML) 6 Page - Texas Instruments |
6 / 33 page LF198-N, LF298, LF398-N LF198A-N, LF398A-N SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015 www.ti.com 6.5 Electrical Characteristics, LF398-N The following specifications apply for –VS + 3.5 V ≤ VIN ≤ +VS – 3.5 V, +VS = +15 V, –VS = –15 V, TA = TJ = 25°C, Ch = 0.01 µF, RL = 10 kΩ, LOGIC REFERENCE = 0 V, LOGIC HIGH = 2.5 V, LOGIC LOW = 0 V unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TJ = 25°C 2 7 mV Input offset voltage(1) Full temperature range 10 mV TJ = 25°C 10 50 nA Input bias current(1) Full temperature range 100 nA Input impedance TJ = 25°C 10 G Ω TJ = 25°C, RL= 10 k 0.004% 0.01% Gain error Full temperature range 0.02% Feedthrough attenuation ratio at 1 kHz TJ = 25°C, Ch = 0.01 µF 80 90 dB TJ = 25°C, “HOLD” mode 0.5 4 Ω Output impedance Full temperature range 6 Ω HOLD step(2) TJ = 25°C, Ch = 0.01 µF, VOUT = 0 1 2.5 mV Supply current(1) TJ ≥ 25°C 4.5 6.5 mA Logic and logic reference input current TJ = 25°C 2 10 µA Leakage current into hold capacitor(1) TJ = 25°C (3), hold mode 30 200 pA ΔVOUT = 10 V, Ch = 1000 pF 4 µs Acquisition time to 0.1% CH = 0.01 µF 20 µs Hold capacitor charging current VIN – VOUT = 2 V 5 mA Supply voltage rejection ratio VOUT = 0 80 110 dB Differential logic threshold TJ = 25°C 0.8 1.4 2.4 V TJ = 25°C 2 2 mV Input offset voltage(1) Full temperature range 3 mV TJ = 25°C 10 25 nA Input bias current(1) Full temperature range 50 nA Input impedance TJ = 25°C 10 G Ω TJ = 25°C, RL = 10 k 0.004% 0.005% Gain error Full temperature range 0.01% Feedthrough attenuation ratio at 1 kHz TJ = 25°C, Ch = 0.01 µF 86 90 dB TJ = 25°C, “HOLD” mode 0.5 1 Ω Output impedance Full temperature range 6 Ω HOLD step(2) TJ = 25°C, Ch = 0.01 µF, VOUT = 0 1 1 mV Supply current(1) TJ ≥ 25°C 4.5 6.5 mA Logic and logic reference input current TJ = 25°C 2 10 µA Leakage current into hold capacitor(1) TJ = 25°C (3), hold mode 30 100 pA ΔVOUT = 10 V, Ch = 1000 pF 4 6 µs Acquisition time to 0.1% CH = 0.01 µF 20 25 µs Hold capacitor charging current VIN – VOUT = 2 V 5 mA Supply voltage rejection ratio VOUT = 0 90 110 dB Differential logic threshold TJ = 25°C 0.8 1.4 2.4 V (1) These parameters ensured over a supply voltage range of ±5 to ±18 V, and an input range of –VS + 3.5 V ≤ VIN ≤ +VS – 3.5 V. (2) Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an additional 0.5-mV step with a 5-V logic swing and a 0.01-µF hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor value. (3) Leakage current is measured at a junction temperature of 25°C. The effects of junction temperature rise due to power dissipation or elevated ambient can be calculated by doubling the 25°C value for each 11°C increase in chip temperature. Leakage is guaranteed over full input signal range. 6 Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N |
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