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SN74ABT3611 Arkusz danych(PDF) 5 Page - Texas Instruments

Numer części SN74ABT3611
Szczegółowy opis  CLOCKED FIRST-IN, FIRST-OUT MEMORY
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SN74ABT3611 Arkusz danych(HTML) 5 Page - Texas Instruments

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SN74ABT3611
64
× 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
A0 – A35
I/O
Port-A data. The 36-bit bidirectional data port for side A.
AE
O
Almost-empty flag. Programmable flag synchronized to CLKB. AE is low when the number of words in the FIFO is less
than or equal to the value in the offset register, X.
AF
O
Almost-full flag. Programmable flag synchronized to CLKA. AF is low when the number of empty locations in the FIFO
is less than or equal to the value in the offset register, X.
B0 – B35
I/O
Port-B data. The 36-bit bidirectional data port for side B.
CLKA
I
Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
or coincident to CLKB. FF and AF are synchronized to the low-to-high transition of CLKA.
CLKB
I
Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous
or coincident to CLKA. EF and AE are synchronized to the low-to-high transition of CLKB.
CSA
I
Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The
A0 – A35 outputs are in the high-impedance state when CSA is high.
CSB
I
Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The
B0 – B35 outputs are in the high-impedance state when CSB is high.
EF
O
Empty flag. EF is synchronized to the low-to-high transition of CLKB. When EF is low, the FIFO is empty and reads from
its memory are disabled. Data can be read from the FIFO to its output register when EF is high. EF is forced low when
the device is reset and is set high by the second low-to-high transition of CLKB after data is loaded into empty FIFO
memory.
ENA
I
Port-A enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A.
ENB
I
Port-B enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.
FF
O
Full flag. FF is synchronized to the low-to-high transition of CLKA. When FF is low, the FIFO is full and writes to its
memory are disabled. FF is forced low when the device is reset and is set high by the second low-to-high transition of
CLKA after reset.
FS1, FS0
I
Flag-offset selects. The low-to-high transition of RST latches the values of FS0 and FS1, which loads one of four preset
values into the almost-full and almost-empty offset register, X.
MBA
I
Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation.
MBB
I
Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the
B0 – B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects
the FIFO output register data for output.
MBF1
O
Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. Writes
to the mail1 register are inhibited while MBF1 is low. MBF1 is set high by a low-to-high transition of CLKB when a port-B
read is selected and MBB is high. MBF1 is set high when the device is reset.
MBF2
O
Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. Writes
to the mail2 register are inhibited while MBF2 is low. MBF2 is set high by a low-to-high transition of CLKA when a port-A
read is selected and MBA is high. MBF2 is set high when the device is reset.
ODD/
EVEN
I
Odd/even parity select. Odd parity is checked on each port when ODD/EVEN is high and even parity is checked when
ODD/EVEN is low. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled
for a read operation.
PEFA
O
(port A)
Port-A parity error flag. When any byte applied to A0 – A35 fails parity, PEFA is low. Bytes are organized as A0 – A8,
A9 – A17, A18 – A26, and A27 – A35, with the most-significant bit of each byte serving as the parity bit. The type of parity
checked is determined by the state of ODD/EVEN.
The parity trees used to check the A0 – A35 inputs are shared by the mail2 register to generate parity if parity generation
is selected by PGA. Therefore, if a mail2 read with parity generation is set up by having CSA low, ENA high, W/RA low,
MBA high, and PGA high, PEFA is forced high, regardless of the state of the A0 – A35 inputs.


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