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SN74V245-15PAGEP Arkusz danych(PDF) 7 Page - Texas Instruments |
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SN74V245-15PAGEP Arkusz danych(HTML) 7 Page - Texas Instruments |
7 / 42 page SN74V245-EP www.ti.com SCAS932A – DECEMBER 2012 – REVISED JANUARY 2013 TIMING REQUIREMENTS MIN MAX UNIT fclock Clock cycle frequency 66.7 MHz tA Data access time 1 11 ns tCLK Clock cycle time 16 ns tCLKH Clock high time 7 ns tCLKL Clock low time 7 ns tDS Data setup time 5 ns tDH Data hold time 2 ns tENS Enable setup time 5 ns tENH Enable hold time 2 ns tLDS Load setup time 5 ns tLDH Load hold time 2 ns tRS Reset pulse width(1) 16 ns tRSS Reset setup time 10.5 ns tRSR Reset recovery time 10.5 ns tRSF Reset to flag and output time 16 ns tOLZ Output enable to output in low Z 0 ns tOE Output enable to output valid 1.5 9 ns tOHZ Output enable to output in high Z 1.5 9 ns tWFF Write clock to Full flag 11 ns tREF Read clock to Empty flag 11 ns tPAFA Clock to asynchronous programmable Almost-Full flag 21 ns tPAFS Write clock to synchronous programmable Almost-Full flag 11 ns tPAEA Clock to asynchronous programmable Almost-Empty flag 21 ns tPAES Read clock to synchronous programmable Almost-Empty flag 11 ns tHF Clock to Half-Full flag 21 ns tXO Clock to expansion out 11 ns tXI Expansion in pulse duration 7 ns tXIS Expansion in setup time 6 ns tSKEW1 Skew time between read clock and write clock for FF/IR and EF/OR 6.5 ns tSKEW2 Skew time between read clock and write clock for PAE and PAF (synchronous only) 18.5 ns (1) Pulse durations less than minimum values are not allowed. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: SN74V245-EP |
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