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SN74V245-15PAGEP Arkusz danych(PDF) 8 Page - Texas Instruments |
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SN74V245-15PAGEP Arkusz danych(HTML) 8 Page - Texas Instruments |
8 / 42 page From Output Under Test 30 pF (see Note A) 510 Ω 330 Ω 3.3 V Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load for tCLK = 10 ns, 15 ns Output Load for tCLK = 7.5 ns GND to 3.0 V 3 ns 1.5 V 1.5 V See A See B and C AC TEST CONDITIONS 50 Ω VCC/2 ZO = 50 Ω I/O B. AC TEST LOAD FOR 7.5 SPEED GRADE A. OUTPUT LOAD CIRCUIT FOR 10, 15, AND 20 SPEED GRADES 0 1 2 3 4 5 6 0 20 40 60 80 100 120 140 160 180 200 C. LUMPED CAPACITIVE LOAD, TYPICAL DERATING Capacitance – pF SN74V245-EP SCAS932A – DECEMBER 2012 – REVISED JANUARY 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION A. Includes probe and jig capacitance Figure 2. Load Circuits 8 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: SN74V245-EP |
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