TP3054-X, TP3057-X

www.ti.com

SNOSBY2C – MARCH 2005 – REVISED APRIL 2013

Extended Temperature Serial Interface CODEC/Filter COMBO Family

Check for Samples: TP3054-X, TP3057-X

1

FEATURES

DESCRIPTION

The TP3054, TP3057 family consists of

μ-law and A-

2

•

−40°C to +85°C Operation

law monolithic PCM CODEC/filters utilizing the A/D

•

Complete CODEC and Filtering System

and D/A conversion architecture shown in Figure 3,

(COMBO) Including:

and a serial PCM interface. The devices are

–

Transmit High-Pass and Low-Pass Filtering

fabricated using TI's advanced double-poly CMOS

process (microCMOS).

–

Receive Low-Pass Filter with Sin x/x

Correction

The encode portion of each device consists of an

input gain adjust amplifier, an active RC pre-filter

–

Active RC Noise Filters

which eliminates very high frequency noise prior to

–

μ-Law or A-Law Compatible COder and

entering a switched-capacitor band-pass filter that

DECoder

rejects signals below 200 Hz and above 3400 Hz.

–

Internal Precision Voltage Reference

Also

included

are

auto-zero

circuitry

and

a

companding coder which samples the filtered signal

–

Serial I/O Interface

and encodes it in the companded

μ-law or A-law

–

Internal Auto-Zero Circuitry

PCM format. The decode portion of each device

•

μ-Law, 16-Pin - TP3054

consists of an expanding decoder, which reconstructs

the analog signal from the companded

μ-law or A-law

•

A-Law, 16-Pin - TP3057

code, a low-pass filter which corrects for the sin x/x

•

Designed for D3/D4 and CCITT Spplications

response of the decoder output and rejects signals

•

±5V Operation

above 3400 Hz followed by a single-ended power

•

Low Operating Power - Typically 50 mW

amplifier capable of driving low impedance loads. The

devices require two 1.536 MHz, 1.544 MHz or

•

Power-Down Standby Mode - Typically 3 mW

2.048 MHz transmit and receive master clocks, which

•

Automatic Power-Down

may be asynchronous; transmit and receive bit

•

TTL or CMOS Compatible Digital Interfaces

clocks, which may vary from 64 kHz to 2.048 MHz;

and transmit and receive frame sync pulses. The

•

Maximizes Line Interface Card Circuit Density

timing of the frame sync pulses and PCM data is

•

Dual-In-Line or PCC Surface Mount Packages

compatible with both industry standard formats.

•

See also AN-370, “Techniques for Designing

with CODEC/Filter COMBO Circuits”

(SNLA136)

Connection Diagram

Figure 1. Plastic Chip Carriers (Top View)

Figure 2. Dual-In-Line Package (Top View)

Package Number FN0020A

Package Number NFG001E & DW0016B

1

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2

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PRODUCTION DATA information is current as of publication date.

Copyright © 2005–2013, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.