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TP3054WM-X Arkusz danych(PDF) 4 Page - Texas Instruments |
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TP3054WM-X Arkusz danych(HTML) 4 Page - Texas Instruments |
4 / 22 page TP3054-X, TP3057-X SNOSBY2C – MARCH 2005 – REVISED APRIL 2013 www.ti.com ASYNCHRONOUS OPERATION For asynchronous operation, separate transmit and receive clocks may be applied. MCLKX and MCLKR must be 2.048 MHz for the TP3057, or 1.536 MHz, 1.544 MHz for the TP3054, and need not be synchronous. For best transmission performance, however, MCLKR should be synchronous with MCLKX, which is easily achieved by applying only static logic levels to the MCLKR/PDN pin. This will automatically connect MCLKX to all internal MCLKR functions (see Pin Description above). For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame. FSX starts each encoding cycle and must be synchronous with MCLKX and BCLKX. FSR starts each decoding cycle and must be synchronous with BCLKR. BCLKR must be a clock, the logic levels shown in Table 1 are not valid in asynchronous mode. BCLKX and BCLKR may operate from 64 kHz to 2.048 MHz. SHORT FRAME SYNC OPERATION The COMBO can utilize either a short frame sync pulse or a long frame sync pulse. Upon power initialization, the device assumes a short frame mode. In this mode, both frame sync pulses, FSX and FSR, must be one bit clock period long, with timing relationships specified in Figure 4. With FSX high during a falling edge of BCLKX, the next rising edge of BCLKX enables the DX TRI-STATE output buffer, which will output the sign bit. The following seven rising edges clock out the remaining seven bits, and the next falling edge disables the DX output. With FSR high during a falling edge of BCLKR (BCLKX in synchronous mode), the next falling edge of BCLKR latches in the sign bit. The following seven falling edges latch in the seven remaining bits. All four devices may utilize the short frame sync pulse in synchronous or asynchronous operating mode. LONG FRAME SYNC OPERATION To use the long frame mode, both the frame sync pulses, FSX and FSR, must be three or more bit clock periods long, with timing relationships specified in Figure 5. Based on the transmit frame sync, FSX, the COMBO will sense whether short or long frame sync pulses are being used. For 64 kHz operation, the frame sync pulse must be kept low for a minimum of 160 ns. The DX TRI-STATE output buffer is enabled with the rising edge of FSX or the rising edge of BCLKX, whichever comes later, and the first bit clocked out is the sign bit. The following seven BCLKX rising edges clock out the remaining seven bits. The DX output is disabled by the falling BCLKX edge following the eighth rising edge, or by FSX going low, whichever comes later. A rising edge on the receive frame sync pulse, FSR, will cause the PCM data at DR to be latched in on the next eight falling edges of BCLKR (BCLKX in synchronous mode). All four devices may utilize the long frame sync pulse in synchronous or asynchronous mode. In applications where the LSB bit is used for signalling, with FSR two bit clock periods long, the decoder will interpret the lost LSB as “½” to minimize noise and distortion. TRANSMIT SECTION The transmit section input is an operational amplifier with provision for gain adjustment using two external resistors, see Figure 8. The low noise and wide bandwidth allow gains in excess of 20 dB across the audio passband to be realized. The op amp drives a unity-gain filter consisting of RC active pre-filter, followed by an eighth order switched-capacitor bandpass filter clocked at 256 kHz. The output of this filter directly drives the encoder sample-and-hold circuit. The A/D is of companding type according to μ-law (TP3054) or A-law (TP3057) coding conventions. A precision voltage reference is trimmed in manufacturing to provide an input overload (tMAX) of nominally 2.5V peak (see Transmission Characteristics). The FSX frame sync pulse controls the sampling of the filter output, and then the successive-approximation encoding cycle begins. The 8-bit code is then loaded into a buffer and shifted out through DX at the next FSX pulse. The total encoding delay will be approximately 165 μs (due to the transmit filter) plus 125 μs (due to encoding delay), which totals 290 μs. Any offset voltage due to the filters or comparator is cancelled by sign bit integration. 4 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: TP3054-X TP3057-X |
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