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TP3054WM-X63SN Arkusz danych(PDF) 3 Page - Texas Instruments

Numer części TP3054WM-X63SN
Szczegółowy opis  Extended Temperature Serial Interface CODEC/Filter COMBO Family
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TP3054-X, TP3057-X
www.ti.com
SNOSBY2C – MARCH 2005 – REVISED APRIL 2013
PIN DESCRIPTIONS (continued)
Symbol
Function
DX
The TRI-STATE PCM data output which is enabled by FSX.
TSX
Open drain output which pulses low during the encoder time slot.
GSX
Analog output of the transmit input amplifier. Used to externally set gain.
VFXI
Inverting input of the transmit input amplifier.
VFXI
+
Non-inverting input of the transmit input amplifier.
Functional Description
POWER-UP
When power is first applied, power-on reset circuitry initializes the COMBO and places it into a power-down
state. All non-essential circuits are deactivated and the DX and VFRO outputs are put in high impedance states.
To power-up the device, a logical low level or clock must be applied to the MCLKR/PDN pin and FSX and/or FSR
pulses must be present. Thus, 2 power-down control modes are available. The first is to pull the MCLKR/PDN pin
high; the alternative is to hold both FSX and FSR inputs continuously low—the device will power-down
approximately 1 ms after the last FSX or FSR pulse. Power-up will occur on the first FSX or FSR pulse. The TRI-
STATE PCM data output, DX, will remain in the high impedance state until the second FSX pulse.
SYNCHRONOUS OPERATION
For synchronous operation, the same master clock and bit clock should be used for both the transmit and receive
directions. In this mode, a clock must be applied to MCLKX and the MCLKR/PDN pin can be used as a power-
down control. A low level on MCLKR/PDN powers up the device and a high level powers down the device. In
either case, MCLKX will be selected as the master clock for both the transmit and receive circuits. A bit clock
must also be applied to BCLKX and the BCLKR/CLKSEL can be used to select the proper internal divider for a
master clock of 1.536 MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation, the device automatically
compensates for the 193rd clock pulse each frame.
With a fixed level on the BCLKR/CLKSEL pin, BCLKX will be selected as the bit clock for both the transmit and
receive directions. Table 1 indicates the frequencies of operation which can be selected, depending on the state
of BCLKR/CLKSEL. In this synchronous mode, the bit clock, BCLKX, may be from 64 kHz to 2.048 MHz, but must
be synchronous with MCLKX.
Each FSX pulse begins the encoding cycle and the PCM data from the previous encode cycle is shifted out of the
enabled DX output on the positive edge of BCLKX. After 8 bit clock periods, the TRI-STATE DX output is returned
to a high impedance state. With an FSR pulse, PCM data is latched via the DR input on the negative edge of
BCLKX (or BCLKR if running). FSX and FSR must be synchronous with MCLKX/R.
Table 1. Selection of Master Clock Frequencies
Master Clock
BCLKR/CLKSEL
Frequency Selected
TP3057
TP3054
Clocked
2.048 MHz
1.536 MHz or 1.544 MHz
0
1.536 MHz or 1.544 MHz
2.048 MHz
1
2.048 MHz
1.536 MHz or 1.544 MHz
Copyright © 2005–2013, Texas Instruments Incorporated
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Product Folder Links: TP3054-X TP3057-X


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