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TPA0162 Arkusz danych(PDF) 3 Page - Texas Instruments |
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TPA0162 Arkusz danych(HTML) 3 Page - Texas Instruments |
3 / 36 page www.ti.com ABSOLUTE MAXIMUM RATINGS TPA0162 SLOS249E – JUNE 1999 – REVISED SEPTEMBER 2004 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. BYPASS 11 Tap to voltage divider for internal mid-supply bias generator If a 47-nF capacitor is attached, the TPA0162 generates an internal clock. An external clock can CLK 17 I override the internal clock input to this terminal. A momentary pulse on this terminal decreases the volume level by 2 dB. Holding the terminal low for a DOWN 3 I period of time will step the amplifier through the volume levels at a rate determined by the capacitor on the CLK terminal. 1, 12 GND I Ground connection for circuitry. Connected to thermal pad 13, 24 LHPIN 6 I Left-channel headphone input, selected when SE/BTL is held high LIN 10 I Common left input for fully differential input. AC ground for single-ended inputs LLINEIN 5 I Left-channel line negative input, selected when SE/BTL is held low LOUT+ 4 O Left-channel positive output in BTL mode and positive in SE mode LOUT- 9 O Left-channel negative output in BTL mode and high impedance in SE mode The input for PC-Beep mode. PC-BEEP is enabled when a > 1.5-V (peak-to-peak) square wave is PC-BEEP 14 I input to PC-BEEP or PCB ENABLE is high. PVDD 7, 18 I Power supply for output stage RHPIN 20 I Right-channel headphone input, selected when SE/BTL is held high RIN 8 I Common right input for fully differential input. AC ground for single-ended inputs RLINEIN 23 I Right-channel line input, selected when SE/BTL is held low. ROUT+ 21 O Right-channel positive output in BTL mode and positive in SE mode ROUT- 16 O Right-channel negative output in BTL mode and high impedance in SE mode Input- and output-MUX control. When this terminal is held high, the LHPIN or RHPIN and SE output is SE/BTL 15 I selected. When this terminal is held low, the LLINEIN or RLINEIN and BTL output are selected. When held low, this terminal places the entire device, except PC-BEEP detect circuitry, in shutdown SHUTDOWN 22 I mode. A momentary pulse on this terminal increases the volume level by 2 dB. Holding the terminal low for a UP 2 I period of time steps the amplifier through the volume levels at a rate determined by the capacitor on the CLK terminal. VDD 19 I Analog VDD input supply. This terminal must be isolated from PVDD to achieve highest performance. Thermal Pad Connect to ground. Must be soldered down in all applications to properly secure device on PC board. over operating free-air temperature range (unless otherwise noted)(1)(1) UNIT Supply voltage, VDD 6 V Input voltage, VI –0.3 V to VDD 0.3 V Continuous total power dissipation Internally limited (see Dissipation Rating Table) Operating free-air temperature range, TA –40 °C to 85°C Operating junction temperature range, TJ –40 °C to 150°C Storage temperature range, Tstg –65 °C to 85°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C (1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 3 |
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