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TPA3136D2PWP Arkusz danych(PDF) 4 Page - Texas Instruments |
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TPA3136D2PWP Arkusz danych(HTML) 4 Page - Texas Instruments |
4 / 35 page 4 TPA3136D2 SLOS938B – MAY 2016 – REVISED JUNE 2016 www.ti.com Product Folder Links: TPA3136D2 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Pin Functions (continued) PIN I/O/P(1) DESCRIPTION NAME NUMBER PBTL 14 I Parallel BTL mode select pin. L=Stereo BTL mode, H=Mono PBTL mode PVCC 15, 16 P Power supply for right channel H-bridge. Right channel and left channel power supply inputs are connected internally. BSPR 17 I Bootstrap I/O for right channel, positive high-side FET. OUTPR 18 O Class-D H-bridge positive output for right channel. GND 19 P Power ground for the H-bridges. OUTNR 20 O Class-D H-bridge negative output for right channel. BSNR 21 I Bootstrap I/O for right channel, negative high-side FET. BSNL 22 I Bootstrap I/O for left channel, negative high-side FET. OUTNL 23 O Class-D H-bridge negative output for left channel. GND 24 P Power ground for the H-bridges. OUTPL 25 O Class-D H-bridge positive output for left channel. BSPL 26 I Bootstrap I/O for left channel, positive high-side FET. PVCC 27, 28 P Power supply for left channel H-bridge. Right channel and left channel power supply inputs are connected internally. Thermal Pad P Connect to GND for best thermal and electrical performance |
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