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ST49C101ACF8-07 Arkusz danych(PDF) 4 Page - Exar Corporation

Numer części ST49C101ACF8-07
Szczegółowy opis  High Frequency Clock Multiplier
Download  10 Pages
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Producent  EXAR [Exar Corporation]
Strona internetowa  http://www.exar.com
Logo EXAR - Exar Corporation

ST49C101ACF8-07 Arkusz danych(HTML) 4 Page - Exar Corporation

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ST49C101A-XX
4
Rev. 2.20
MULTIPLICATION FACTOR AND OUTPUT FRE-
QUENCY SELECTION
The ST49C101A-XX contains an analog phase locked
loop (PLL) circuit with digital closed loop dividers and
a final output divider to achieve the desired dividing
ratios for the clock output. The preprogrammed multi-
plication factor and output frequency are shown on
Table 1. The accuracy of the output frequency pro-
duced by the ST49C101A-XX depends on its input
frequency and multiplication factor.
APPLICATIONS
Two application examples are shown in Figure 2 and 3.
Figure 2 shows a lower cost high frequency crystal
oscillator circuit using the ST49C101-xx to increase
the fundamental crystal frequency. The crystal Y1 is
connected to XTAL1 and XTAL2 pins to use the
internal oscillator circuit. The oscillator provides the
reference clock to the PLL circuit for clock rate multi-
plication. Figure 3 shows a similar circuit using
external clock input on XTAL1 pin instead.
If a sinewave is used for external clock, it may be
necessary to AC couple the signal with a 0.047uF
capacitor to XTAL1 pin so that the internal circuitry
can establish the proper bias. Also, keep the peak-to-
peak signal, at XTAL pin, above ground level (AGND)
and below AVCC.
As a general board layout rule, it is recommended to
use two 0.01
µF bypass capacitors on DVCC and
AVCC power supply pins, and put them as closely as
possible to the chip.
Notes
1See AC electrical characteristics for maximum operating
frequency.
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