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GS1660A Arkusz danych(PDF) 9 Page - Semtech Corporation

Numer części GS1660A
Szczegółowy opis  HD/SD SDI Receiver Complete with SMPTE Video Processing
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Producent  SEMTECH [Semtech Corporation]
Strona internetowa  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

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GS1660A HD/SD SDI Receiver Complete with SMPTE
Video Processing
Data Sheet
54386 - 3
September 2012
9 of 83
B1
A_VDD
Input Power
POWER pin for analog circuitry. Connect to 3.3V DC analog.
B2, C3, C4
PLL_VDD
Input Power
POWER pins for the Reclocker PLL. Connect to 1.2V DC analog.
B3, F2, G1,
G2
RSV
These pins must be left unconnected.
B4
VCO_GND
Input Power
GND pin for the VCO. Connect to analog GND.
B7, D9, G9,
J7
IO_GND
Input Power
GND connection for digital I/O. Connect to digital GND.
C1, D1
SDI, SDI
Analog Input
Serial Digital Differential Input.
C2, D2, D3,
E3, F3
A_GND
Input Power
GND pins for sensitive analog circuitry. Connect to analog GND.
C7RESET_TRST
Input
CONTROL SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to reset the internal operating conditions to default settings
and to reset the JTAG sequence.
Normal mode (JTAG/HOST = LOW):
When LOW, all functional blocks are set to default conditions and
all digital output signals become high impedance.
When HIGH, normal operation of the device resumes.
JTAG test mode (JTAG/HOST = HIGH):
When LOW, all functional blocks are set to default and the JTAG test
sequence is reset.
When HIGH, normal operation of the JTAG test sequence resumes
after RESET_TRST is de-asserted.
D4, E4, F4
PLL_GND
Input Power
GND pins for the Reclocker PLL. Connect to analog GND.
D5, E5, F5,
G4, G5
CORE_GND
Input Power
GND connection for device core. Connect to digital GND.
D6, E6, F6,
G6
CORE_VDD
Input Power
POWER connection for device core. Connect to 1.2V DC digital.
D7
SW_EN
Input
CONTROL SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to enable switch-line locking, as described in Section 4.9.1.
D8
JTAG/HOST
Input
CONTROL SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to select JTAG test mode or host interface mode.
When JTAG/HOST is HIGH, the host interface port is configured for
JTAG test.
When JTAG/HOST is LOW, normal operation of the host interface
port resumes.
E1
SDI_VDD
Input Power
POWER pin for SDI buffer. Connect to 3.3V DC analog.
Table 1-1:Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description


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