GS1671A datasheet(6/136 Pages) SEMTECH

Numer części	GS1671A

Szczegółowy opis	HD/SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with SMPTE Audio and Video Processing

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Producent	SEMTECH [Semtech Corporation]

Strona internetowa	http://www.semtech.com

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6 / 136 page

GS1671A HD/SD SDI Receiver

Data Sheet

54389 - 1

September 2012

6 of 136

List of Figures

Figure 3-1: Digital Input Pin with Schmitt Trigger............................................................................... 23

Figure 3-2: Bidirectional Digital Input/Output Pin..............................................................................23

Figure 3-3: Bidirectional Digital Input/Output Pin with programmable drive strength ........ 24

Figure 3-4: XTAL1/XTAL2/XTAL-OUT ................................................................................................... 24

Figure 3-5: VBG .............................................................................................................................................. 24

Figure 3-6: LB_CONT .................................................................................................................................... 25

Figure 3-7: Loop Filter .................................................................................................................................. 25

Figure 3-8: SDO/SDO .................................................................................................................................... 25

Figure 3-9: Equalizer Input Equivalent Circuit .................................................................................... 25

Figure 4-1: GS1671A Integrated EQ Block Diagram .......................................................................... 28

Figure 4-2: 27MHz Clock Sources ............................................................................................................ 30

Figure 4-3: PCLK to Data and Control Signal Output Timing - SDR Mode 1 .............................. 34

Figure 4-4: PCLK to Data and Control Signal Output Timing - SDR Mode 2 .............................. 35

Figure 4-5: Switch Line Locking on a Non-Standard Switch Line ................................................. 39

Figure 4-6: H:V:F Output Timing - HDTV 20-bit Mode ..................................................................... 43

Figure 4-7: H:V:F Output Timing - HDTV 10-bit Mode ..................................................................... 43

Figure 4-8: H:V:F Output Timing - HD 20-bit Output Mode ............................................................ 43

Figure 4-9: H:V:F Output Timing - HD 10-bit Output Mode ............................................................ 44

Figure 4-10: H:V:F Output Timing - SD 20-bit Output Mode .......................................................... 44

Figure 4-11: H:V:F Output Timing - SD 10-bit Output Mode .......................................................... 44

Figure 4-12: H:V:DE Output Timing 1280 x 720p @ 59.94/60 (Format 4) ................................... 46

Figure 4-13: H:V:DE Output Timing 1920 x 1080i @ 59.94/60 (Format 5) ................................. 46

Figure 4-14: H:V:DE Output Timing 720 (1440) x 480i @ 59.94/60 (Format 6&7) .................... 47

Figure 4-15: H:V:DE Output Timing 1280 x 720p @ 50 (Format 19) ............................................. 47

Figure 4-16: H:V:DE Output Timing 1920 x 1080i @ 50 (Format 20) ........................................... 48

Figure 4-17: H:V:DE Output Timing 720 (1440) x 576 @ 50 (Format 21 & 22) ........................... 49

Figure 4-18: H:V:DE Output Timing 1920 x 1080p @ 23.94/24 (Format 32) .............................. 49

Figure 4-19: H:V:DE Output Timing 1920 x 1080p @ 25 (Format 33) .......................................... 50

Figure 4-20: H:V:DE Output Timing 1920 x 1080p @ 29.97/30 (Format 34) .............................. 50

Figure 4-21: 2K Feature Enhancement ................................................................................................... 53

Figure 4-22: Y/1ANC and C/2ANC Signal Timing .............................................................................. 60

Figure 4-23: Ancillary Data Extraction - Step A .................................................................................. 66

Figure 4-24: Ancillary Data Extraction - Step B ................................................................................... 67

Figure 4-25: Ancillary Data Extraction - Step C .................................................................................. 67

Figure 4-26: Ancillary Data Extraction - Step D .................................................................................. 68

Figure 4-27: ACLK to Data Signal Output Timing ............................................................................... 70

Figure 4-28: I2S Audio Output Format .................................................................................................... 71

Figure 4-29: AES/EBU Audio Output Format .......................................................................................71

Figure 4-30: Serial Audio, Left Justified, MSB First ............................................................................. 72

Figure 4-31: Serial Audio, Left Justified, LSB First .............................................................................. 72

Figure 4-32: Serial Audio, Right Justified, MSB First ..........................................................................72

Figure 4-33: Serial Audio, Right Justified, LSB First ........................................................................... 72

Figure 4-34: AES/EBU Audio Output to Bit Clock Timing ................................................................ 72

Figure 4-35: ECC 24-bit Array and Examples ...................................................................................... 75

Figure 4-36: Sample Distribution Over Five Video Frames (525-line Systems) ........................ 76

Figure 4-37: Audio Buffer After Initial 26 Sample Write .................................................................. 77

Figure 4-38: Audio Buffer Pointer Boundary Checking .................................................................... 77

Figure 4-39: GSPI Application Interface Connection ........................................................................ 83

Figure 4-40: Command Word Format ..................................................................................................... 83

Figure 4-41: Data Word Format ................................................................................................................ 84

Figure 4-42: Write Mode .............................................................................................................................. 85

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