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MC10H180L Arkusz danych(PDF) 1 Page - ON Semiconductor |
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MC10H180L Arkusz danych(HTML) 1 Page - ON Semiconductor |
1 / 4 page © Semiconductor Components Industries, LLC, 2000 March, 2000 – Rev. 6 1 Publication Order Number: MC10H180/D MC10H180 Dual 2-Bit Adder/Subtractor The MC10H180 is a high–speed, low–power, general–purpose adder/ subtractor. It is designed to be used in special purpose adders/subtractors or in high–speed multiplier arrays. Inputs for each adder are Carry–in, Operand A, and Operand B; outputs are Sum, Sum and Carry–out. The common select inputs serve as a control line to Invert A for subtract, and a control line to Invert B. • Propagation Delay, 1.8 ns Typical, Operand and Select to Output • Power Dissipation, 360 mW Typicalh180 • Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range) • Voltage Compensated • MECL 10K–Compatible LOGIC DIAGRAM DIP PIN ASSIGNMENT S1 S0 COUT CIN A0 B0 SELA VEE VCC S0 S1 COUT CIN A1 B1 SELB 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 10 S1 S0 CIN BO AO SELB SELA VCC = PIN 16 VEE = PIN 8 7 9 5 4 6 15 2 11 12 3 14 1 13 SELA SELB A1 B1 CIN S0 COUT S1 COUT POSITIVE LOGIC ONLY A’ = A SELA = ASELA B’ = B SELB = BSELB S= CIN (A’ B’ + A’ B’) + CIN(A’ B’ + A’ B’) COUT = CINA’ + CINB’ + A’ B’ Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). http://onsemi.com Device Package Shipping ORDERING INFORMATION MC10H180L CDIP–16 25 Units/Rail MC10H180P PDIP–16 25 Units/Rail MC10H180FN PLCC–20 46 Units/Rail MARKING DIAGRAMS 1 16 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week CDIP–16 L SUFFIX CASE 620 MC10H180L AWLYYWW PDIP–16 P SUFFIX CASE 648 PLCC–20 FN SUFFIX CASE 775 10H180 AWLYYWW 1 1 16 MC10H180P AWLYYWW |
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