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MC100EP33DR2 Arkusz danych(PDF) 2 Page - ON Semiconductor |
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MC100EP33DR2 Arkusz danych(HTML) 2 Page - ON Semiconductor |
2 / 12 page MC10EP33, MC100EP33 http://onsemi.com 2 1 2 3 45 6 7 8 Q VEE VCC Figure 1. 8–Lead Pinout (Top View) and Logic Diagram CLK Q CLK VBB RESET R B4 PIN DESCRIPTION PIN CLK*, CLK* Reset* ECL Asynchronous Reset FUNCTION ECL Clock Inputs TRUTH TABLE CLK X Z CLK X Z RESET Z L Q L F Q H F Z = LOW to HIGH Transition Z = HIGH to LOW Transition F = Divide by 4 Function VBB Reference Voltage Output Q, Q ECL Data Outputs VCC Positive Supply VEE Negative Supply * Pins will default LOW when left open. Figure 2. Timing Diagram CLK RESET Q tRR ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k W Internal Input Pullup Resistor NA ESD Protection Human Body Model Machine Model Charged Device Model > 4 kV > 200 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Level 1 Flammability Rating Oxygen Index: 28 to 34 UL–94 V–0 @ 0.125 in Transistor Count 91 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. |
Podobny numer części - MC100EP33DR2 |
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Podobny opis - MC100EP33DR2 |
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