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MC10EP33DTR2 Arkusz danych(PDF) 1 Page - ON Semiconductor |
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MC10EP33DTR2 Arkusz danych(HTML) 1 Page - ON Semiconductor |
1 / 12 page © Semiconductor Components Industries, LLC, 2002 September, 2002 – Rev. 5 1 Publication Order Number: MC10EP33/D MC10EP33, MC100EP33 3.3V / 5VECL B4 Divider The MC10/100EP33 is an integrated B4 divider. The differential clock inputs. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The reset pin is asynchronous and is asserted on the rising edge. Upon power–up, the internal flip–flops will attain a random state; the reset allows for the synchronization of multiple EP33’s in a system. The 100 Series contains temperature compensation. • 320 ps Propagation Delay • Maximum Frequency > 4 GHz Typical • PECL Mode Operating Range: V CC = 3.0 V to 5.5 V with VEE = 0 V • NECL Mode Operating Range: V CC = 0 V with VEE = –3.0 V to –5.5 V • Open Input Default State • Safety Clamp on Inputs • Q Output Will Default LOW with Inputs Open or at V EE • V BB Output Device Package Shipping ORDERING INFORMATION MC10EP33D SO–8 98 Units/Rail MC10EP33DR2 SO–8 2500 Tape & Reel MC100EP33D SO–8 98 Units/Rail MC100EP33DR2 SO–8 2500 Tape & Reel MC10EP33DT TSSOP–8 100 Units/Rail MC10EP33DTR2 TSSOP–8 2500 Tape & Reel MC100EP33DT TSSOP–8 100 Units/Rail MC100EP33DTR2 TSSOP–8 2500 Tape & Reel L = Wafer Lot Y = Year W = Work Week *For additional information, see Application Note AND8002/D H = MC10 K = MC100 A = Assembly Location SO–8 D SUFFIX CASE 751 MARKING DIAGRAMS* TSSOP–8 DT SUFFIX CASE 948R ALYW KEP33 ALYW HP33 HEP33 ALYW ALYW KP33 1 8 1 8 1 8 1 8 1 8 1 8 http://onsemi.com |
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