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MC100EP195BMNR4G Arkusz danych(PDF) 11 Page - ON Semiconductor |
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MC100EP195BMNR4G Arkusz danych(HTML) 11 Page - ON Semiconductor |
11 / 17 page MC100EP195B http://onsemi.com 11 Table 10. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −3.6 V or VCC = 3.0 V to 3.6 V; VEE = 0 V (Note 14) Symbol Unit 85 °C 25 °C −40 °C Characteristic Symbol Unit Max Typ Min Max Typ Min Max Typ Min Characteristic VPP Input Voltage Swing (Differential Configuration) 150 800 1200 150 800 1200 150 800 1200 mV tr tf Output Rise/Fall Time @ 50 MHz 20−80% (Q) 20−80% (CASCADE) 85 110 115 160 140 210 100 120 120 175 140 230 100 120 130 190 165 250 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V. 15. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range. 16. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output. 17. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set. 18. This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than ±75 mV to that IN/IN transition. 19. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output re- sponse greater than ±75 mV to that IN/IN transition. 20. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets the specified IN to Q propagation delay and transition times. 21. Deviation from a linear delay (actual Min to Max) in the 1024 programmable steps. Figure 4. AC Reference Measurement IN IN Q Q tPHL tPLH VINPP = VIH(D) − VIL(D) VOUTPP = VOH(Q) − VOL(Q) Cascading Multiple EP195Bs To increase the programmable range of the EP195B, internal cascade circuitry has been included. This circuitry allows for the cascading of multiple EP195Bs without the need for any external gating. Furthermore, this capability requires only one more address line per added E195B. Obviously, cascading multiple programmable delay chips will result in a larger programmable range: however, this increase is at the expense of a longer minimum delay. Figure 5 illustrates the interconnect scheme for cascading two EP195Bs. As can be seen, this scheme can easily be expanded for larger EP195B chains. The D10 input of the EP195B is the CASCADE control pin. With the interconnect scheme of Figure 5 when D10 is asserted, it signals the need for a larger programmable range than is achievable with a single device and switches output pin CASCADE HIGH and pin CASCADE LOW. The A11 address can be added to generate a cascade output for the next EP195B. For a 2−device configuration, A11 is not required. |
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