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SM320C6424GDUQ6EP Arkusz danych(PDF) 1 Page - Texas Instruments |
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SM320C6424GDUQ6EP Arkusz danych(HTML) 1 Page - Texas Instruments |
1 / 237 page 1 Introduction 1.1 Features SM320C6424-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS580 – JUNE 2009 • High-Performance Digital Signal Processor • C64x+ L1/L2 Memory Architecture (C6424) – 256K-Bit (32K-Byte) L1P Program – 2.5-, 2-, 1.67-, 1.43-ns Instruction Cycle RAM/Cache [Flexible Allocation] Time – 640K-Bit (80K-Byte) L1D Data RAM/Cache – 400-, 500-, 600-, 700-MHz C64x+™ Clock [Flexible Allocation] Rate – 1M-Bit (128K-Byte) L2 Unified Mapped – Eight 32-Bit C64x+ Instructions/Cycle RAM/Cache [Flexible Allocation] – 3200, 4000, 4800, 5600 MIPS • Endianess: Supports Both Little Endian and – Fully Software-Compatible With C64x Big Endian – Commercial and Automotive (Q or S suffix) • External Memory Interfaces (EMIFs) Grades – 32-Bit DDR2 SDRAM Memory Controller – Low-Power Device (L suffix) With 256M-Byte Address Space (1.8-V I/O) • VelociTI.2™ Extensions to VelociTI™ • Supports up to 333-MHz (data rate) bus and interfaces to DDR2-400 SDRAM Advanced Very-Long-Instruction-Word (VLIW) SM320C64x+™ DSP Core – Asynchronous 16-Bit Wide EMIF (EMIFA) With up to 128M-Byte Address Reach – Eight Highly Independent Functional Units With VelociTI.2 Extensions: • Flash Memory Interfaces • Six ALUs (32-/40-Bit), Each Supports – NOR (8-/16-Bit-Wide Data) Single 32-Bit, Dual 16-Bit, or Quad 8-Bit – NAND (8-/16-Bit-Wide Data) Arithmetic per Clock Cycle • Enhanced Direct-Memory-Access (EDMA) • Two Multipliers Support Four 16 x 16-Bit Controller (64 Independent Channels) Multiplies (32-Bit Results) per Clock • Two 64-Bit General-Purpose Timers (Each Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Configurable as Two 32-Bit Timers) Results) per Clock Cycle – Load-Store Architecture With Non-Aligned • One 64-Bit Watch Dog Timer Support • Two UARTs (One with RTS and CTS Flow – 64 32-Bit General-Purpose Registers Control) – Instruction Packing Reduces Code Size • Master/Slave Inter-Integrated Circuit (I2C – All Instructions Conditional Bus™) – Additional C64x+™ Enhancements • Two Multichannel Buffered Serial Ports • Protected Mode Operation (McBSPs) • Exceptions Support for Error Detection – I2S and TDM and Program Redirection – AC97 Audio Codec Interface • Hardware Support for Modulo Loop – SPI Auto-Focus Module Operation – Standard Voice Codec Interface (AIC12) • C64x+ Instruction Set Features – Telecom Interfaces – ST-Bus, H-100 – Byte-Addressable (8-/16-/32-/64-Bit Data) – 128 Channel Mode – 8-Bit Overflow Protection • Multichannel Audio Serial Port (McASP0) – Bit-Field Extract, Set, Clear – Four Serializers and SPDIF (DIT) Mode – Normalization, Saturation, Bit-Counting • 16-Bit Host-Port Interface (HPI) – VelociTI.2 Increased Orthogonality • 32-Bit 33-MHz, 3.3-V Peripheral Component – C64x+ Extensions Interconnect (PCI) Master/Slave Interface • Compact 16-bit Instructions • Additional Instructions to Support Complex Multiplies Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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