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AD9121 Arkusz danych(PDF) 7 Page - Analog Devices

Numer części AD9121
Szczegółowy opis  TxDAC Digital-to-Analog Converter
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Strona internetowa  http://www.analog.com
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AD9121 Arkusz danych(HTML) 7 Page - Analog Devices

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AD9121
Data Sheet
Rev. B | Page 6 of 60
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, maximum sample rate, unless otherwise
noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
CMOS INPUTLOGIC LEVEL
Input VIN Logic High
IOVDD = 1.8 V
1.2
V
IOVDD = 2.5 V
1.6
V
IOVDD = 3.3 V
2.0
V
Input VIN Logic Low
IOVDD = 1.8 V
0.6
V
IOVDD = 2.5 V, 3.3 V
0.8
V
CMOS OUTPUT LOGIC LEVEL
Output VOUT Logic High
IOVDD = 1.8 V
1.4
V
IOVDD = 2.5 V
1.8
V
IOVDD = 3.3 V
2.4
V
Output VOUT Logic Low
IOVDD = 1.8 V, 2.5 V, 3.3 V
0.4
V
LVDS RECEIVER INPUTS1
Applies to data, DCI, and FRAME inputs
Input Voltage Range, VIA or VIB
825
1675
mV
Input Differential Threshold, VIDTH
−100
+100
mV
Input Differential Hysteresis, VIDTHH to VIDTHL
20
mV
Receiver Differential Input Impedance, RIN
80
120
Ω
LVDS Input Rate
See Table 5
DAC CLOCK INPUT (DACCLKP, DACCLKN)
Differential Peak-to-Peak Voltage
100
500
2000
mV
Common-Mode Voltage
Self-biasedinput, ac-coupled
1.25
V
Maximum Clock Rate
1230
MHz
REFCLK INPUT (REFCLKP, REFCLKN)
Differential Peak-to-Peak Voltage
100
500
2000
mV
Common-Mode Voltage
1.25
V
REFCLK Frequency (PLL Mode)
1 GHz ≤ fVCO ≤ 2.1 GHz
15.625
600
MHz
REFCLK Frequency (SYNC Mode)
See the Multichip Synchronization section
for conditions
0
600
MHz
SERIAL PORT INTERFACE
Maximum Clock Rate (SCLK)
40
MHz
Minimum Pulse Width High (tPWH)
12.5
ns
Minimum Pulse Width Low (tPWL)
12.5
ns
Setup Time, SDIO to SCLK (tDS)
1.9
ns
Hold Time, SDIO to SCLK (tDH)
0.2
ns
Data Valid, SDO to SCLK (tDV)
2.3
ns
Setup Time, CS to SCLK (tDCSB)
1.4
ns
1 LVDS receiver is compliant with the IEEE 1596reduced range link, unless otherwisenoted.
DIGITAL INPUT DATA TIMING SPECIFICATIONS
Table 3.
Parameter
Value
Unit
LATENCY (DACCLK CYCLES)
1× Interpolation(Withor Without Modulation)
64
Cycles
2× Interpolation(Withor Without Modulation)
135
Cycles
4× Interpolation(Withor Without Modulation)
292
Cycles
8× Interpolation(Withor Without Modulation)
608
Cycles
Inverse Sinc
20
Cycles
Fine Modulation
8
Cycles


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