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2EDN7524F Arkusz danych(PDF) 8 Page - Infineon Technologies AG |
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2EDN7524F Arkusz danych(HTML) 8 Page - Infineon Technologies AG |
8 / 31 page Data Sheet 8 Revision2.3 2016-10-05 EiceDRIVER™ 2EDN752x / 2EDN852x Pin Configuration and Description The pin configuration for direct input versions of 2EDN7524G and 2EDN7523G in the PG-WSON-8-1 package is shown in Figure 3. Drawings can be viewed in Chapter 8 (PG-WSON-8-1). Figure 3 Pin Configuration PG-WSON-8-1, Top View Table 5 Pin Configuration 2EDN7524G and 2EDN7523G in the PG-WSON-8-1 Package Pin Symbol Description 1 ENA Enable input channel A Logic input; if ENA is high or left open, OUTA is controlled by INA; ENA low causes OUTA low 2 INA Input signal channel A Logic input, controlling OUTA (non-inverting) 3GND Ground1) 1)Exposed Pad of PG-WSON-8-1 packages has to be connected to GND pin. 4 INB Input signal channel B Logic input, controlling OUTB (non-inverting) 5 OUTB Driver output channel B Low-impedance output with source and sink capability 6 VDD Positive supply voltage Operating range 4.5 V/8.6V to 20 V 7 OUTA Driver output channel A Low-impedance output with source and sink capability 8 ENB Enable input channel B Logic Input; if ENB is high or left open, OUTB is controlled by INB; ENB low causes OUTB low 8 7 6 5 ENB OUTA VDD OUTB GND ENA INA INB 2 3 4 1 Exposed Pad |
Podobny numer części - 2EDN7524F_16 |
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Podobny opis - 2EDN7524F_16 |
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