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AD9122SCPZ-EP Arkusz danych(PDF) 7 Page - Analog Devices |
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AD9122SCPZ-EP Arkusz danych(HTML) 7 Page - Analog Devices |
7 / 12 page Enhanced Product AD9122-EP Rev. 0 | Page 7 of 12 The setup (tS) and hold (tH) times, with respect to the edges, are shown in Figure 3. The minimum setup and hold times are shown in Table 6. DCI DATA tDATA tDATA SAMPLING INTERVAL SAMPLING INTERVAL tS tS tH tH Figure 3. Timing Diagram for Input Data Port Table 6. Data to DCI Setup and Hold Times DCI Delay Register 0x16, Bits[1:0] Minimum Setup Time, tS (ns) Minimum Hold Time, tH (ns) Sampling Interval (ns) 00 −0.01 0.65 0.64 01 −0.19 0.95 0.76 10 −0.38 1.22 0.84 11 −0.44 1.38 0.94 The data interface timing can be verified by using the sample error detection (SED) circuitry. See the Interface Timing Validation section in the AD9122 data sheet for more information. |
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