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8V49NS0312NLGI8 Arkusz danych(PDF) 7 Page - Integrated Device Technology |
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8V49NS0312NLGI8 Arkusz danych(HTML) 7 Page - Integrated Device Technology |
7 / 57 page 7 ©2016 Integrated Device Technology, Inc. September 2, 2016 8V49NS0312 Datasheet Principles of Operation The 8V49NS0312 can be locked to either an input reference clock or a 10MHz to 50MHz fundamental-mode crystal and generate a wide range of synchronized output clocks. Lock status may be monitored via the LOCK pin. It could be used for example in either the transmit or receive path of Synchronous Ethernet or SONET/SDH equipment. The 8V49NS0312 accepts a differential or single-ended input clock ranging from 5MHz up to 1GHz. It generates up to twelve output clocks with up to four different output frequencies, ranging from 10.91MHz up to 2.5GHz. The device outputs are divided into 4 output banks. Each bank supports conversion of the input frequency to a different output frequency: one independent or integer-related output frequency on Bank D (QD[0:1]) and three more integer-related frequencies on Bank A (QA[0:3]), Bank B (QB[0:3]) and Bank C (QC[0:1]). All outputs within a bank will have the same frequency. The device is programmable through an I2C serial interface or control input pins. Pin versus Register Control The 8V49NS0312 can be configured by the use of input control pins and/or over an I2C serial port. The pins / registers used to control each function are shown in Table 4. At power-up, control of each function is via the control input pins. Access over the serial port can change each function individually to be controlled by registers. This allows for any mixture of register or pin control. However any of the indicated functions can only be controlled by register or by pin at any given time, not by both. Use of register control will allow access to a wider range of configuration options, but values are lost on power-down. Changes to the control input pins while the part is active are allowed, but can not be guaranteed to be glitch-free. It is recommended that any such changes be performed by disabling the outputs using the I2C-accessible registers, then re-enabling once changes are completed. Also, the output dividers, which are synchronized on power-up will not be re-synchronized without an explicit access to the INIT_CLK register bit over the I2C interface. Any change to the output dividers performed over the I2C interface must be followed by an assertion of the INIT_CLK register bit to force the loading of the new divider values, as well as to synchronize the output dividers. Table 4: Control of Specific Functions Function Control Select Bit Control Input Pins Register Fields Affected Prescaler & PLL Feedback Divider FIN_CTL FIN[1:0] PS[5:0], FDP M[8:0] Bank A Divider & Output Type NA_CTL NA[1:0] NA_DIV, PD_A, EN_A, PD_QAx, STY_QAx, AMP_QAx[1:0] Bank B Divider & Output Type NB_CTL NB[1:0] NB_DIV, PD_B, EN_B, PD_QBx, STY_QBx, AMP_QBx[1:0] Bank C Divider & Output Type NC_CTL NC[1:0] NC_DIV, PD_C, EN_C, PD_QCx, STY_QCx, AMP_QCx[1:0] Bank D Divider & Output Type ND_CTL ND[1:0] ND[5:0], ND_FINT[3:0], ND_FRAC[23:0], ND_DIVF[1:0], ND_SRC[1:0], PD_D, EN_D, PD_QDx, STY_QD0, AMP_QD0[1:0] |
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