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UCS1003-3-BP-TR Arkusz danych(PDF) 5 Page - Microchip Technology |
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UCS1003-3-BP-TR Arkusz danych(HTML) 5 Page - Microchip Technology |
5 / 138 page 2014-2015 Microchip Technology Inc. DS20005346B-page 5 UCS1003-1/2/3 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† Voltage on VDD, VS and VBUS Pins....................................................................................................................-0.3 to 6V Pull-up Voltage (VPULLUP) .................................................................................................................... -0.3 to VDD + 0.3V Data Switch Current (IHSW_ON), Switch On...........................................................................................................±50 mA Port Power Switch Current .................................................................................................................... Internally Limited Data Switch Pin Voltage To Ground (DPOUT, DPIN, DMOUT, DMIN); (VDD powered or unpowered)....... -0.3 to VDD +0.3V Differential Voltage Across Open Data Switch (DPOUT – DPIN, DMOUT – DMIN, DPIN – DPOUT, DMIN – DMOUT) .........VDD Voltage on any Other Pin to Ground ................................................................................................... -0.3 to VDD + 0.3V Current on any Other Pin ......................................................................................................................................±10 mA Package Power Dissipation ............................................................................................................................... Table 1-1 Operating Ambient Temperature Range .....................................................................................................-40 to +125°C Storage Temperature Range.......................................................................................................................-55 to +150°C † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: POWER DISSIPATION SUMMARY Board Package JC JA Derating Factor Above +25°C TA <+25°C Power Rating TA <+70°C Power Rating TA < +85°C Power Rating High K (see Note 1) 20-pin QFN 4x 4 mm 6°C/W 41°C/W 24.4 mW°/C 2193 mW 1095 mW 729 mW Low K (see Note 1) 20-pin QFN 4x 4 mm 6°C/W 60°C/W 16.67 mW°/C 1498 mW 748 mW 498 mW Note 1: Junction to ambient ( JA) is dependent on the design of the thermal vias. A High K board uses a thermal via design with a thermal landing soldered to the PCB ground plane, with 0.3 mm (12 mil) diameter vias in a 3x3 matrix (9 total) at 0.5 mm (20 mil) pitch. The board is multilayer with 1-ounce internal power and ground planes and 2-ounce copper traces on top and bottom. A Low K board is a two-layer board without thermal via design, with 2-ounce copper traces on the top and bottom. |
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