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8T73S208B-01NLGI Arkusz danych(PDF) 1 Page - Integrated Device Technology

Numer części 8T73S208B-01NLGI
Szczegółowy opis  2.5 V, 3.3 V Differential LVPECL Clock Divider and Fanout Buffer
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Producent  IDT [Integrated Device Technology]
Strona internetowa  http://www.idt.com
Logo IDT - Integrated Device Technology

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©2016 Integrated Device Technology, Inc.
April 28, 2016
General Description
The 8T73S208B-01 is a high-performance differential LVPECL clock
divider and fanout buffer. The device is designed for the frequency
division and signal fanout of high-frequency, low phase-noise clocks.
The 8T73S208B-01 is characterized to operate from a 2.5V and 3.3V
power supply. Guaranteed output-to-output and part-to-part skew
characteristics make the 8T73S208B-01 ideal for those clock
distribution applications demanding well-defined performance and
repeatability. The integrated input termination resistors make
interfacing to the reference source easy and reduce passive
component count. Each output can be individually enabled or
disabled in the high-impedance state controlled by a I2C register. On
power-up, all outputs are disabled.
Features
One differential input reference clock
Differential pair can accept the following differential input
levels: LVDS, LVPECL, CML
Integrated input termination resistors
Eight LVPECL outputs
Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
Maximum input clock frequency: 1GHz
LVCMOS interface levels for the control inputs
Individual output enable/disabled by I2C interface
Power-up state: all outputs disabled
Output skew: 60ps (maximum)
Output rise/fall times: 350ps (maximum)
Low additive phase jitter, RMS: 182fs (typical)
Full 2.5V and 3.3V supply voltages
Lead-free (RoHS 6) 32-Lead VFQFN packaging
-40°C to 85°C ambient operating temperature
Block Diagram
Pin Assignment
fREF
8
2
2
IN
nIN
VT
FSEL[1:0]
SDA
SCL
ADR[1:0]
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
÷1, ÷2,
÷4, ÷8
50
50
Pullup
Pullup
Pulldown (2)
Pulldown (2)
I2C
32
1
VCCO
VCCO
VEE
Q6
nQ6
Q7
nQ7
VEE
FSEL0
VEE
nQ1
Q1
nQ0
Q0
VEE
ADR1
2
3
4
5
6
7
8
9
10111213141516
24
23
22
21
20
19
18
17
31 30 29 28 27 26 25
5mm x 5mm, 32-pin VFQFN
2.5 V, 3.3 V Differential LVPECL Clock
Divider and Fanout Buffer
8T73S208B-01
Datasheet


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