9ZXL0831

8-OUTPUT DB800ZL

IDT®

8-OUTPUT DB800ZL

8

9ZXL0831

REV E 081616

Electrical Characteristics–Skew and Differential Jitter Parameters

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

CLK_IN, DIF[x:0]

Input-to-Output Skew in PLL mode

nominal value @ 25°C, 3.3V

-100

-60

100

ps

1,2,4,5,8

CLK_IN, DIF[x:0]

Input-to-Output Skew in Bypass mode

nominal value @ 25°C, 3.3V

2.5

3.2

4.5

ns

1,2,3,5,8

CLK_IN, DIF[x:0]

Input-to-Output Skew Varation in PLL mode

across voltage and temperature

-50

50

ps

1,2,3,5,8

CLK_IN, DIF[x:0]

Input-to-Output Skew Varation in Bypass mode

across voltage and temperature

-250

250

ps

1,2,3,5,8

CLK_IN, DIF[x:0]

Random Differential Tracking error beween two

9ZX devices in Hi BW Mode

15

ps

(rms)

1,2,3,5,8

CLK_IN, DIF[x:0]

Random Differential Spread Spectrum Tracking

error beween two 9ZX devices in Hi BW Mode

5

75

ps

1,2,3,5,8

DIF{x:0]

Output-to-Output Skew across all outputs

(Common to Bypass and PLL mode)

53

65

ps

1,2,3,8

PLL Jitter Peaking

LOBW#_BYPASS_HIBW = 1

0

1.2

2.5

dB

7,8

PLL Jitter Peaking

LOBW#_BYPASS_HIBW = 0

0

0.76

2

dB

7,8

PLL Bandwidth

LOBW#_BYPASS_HIBW = 1

2

3

4

MHz

8,9

PLL Bandwidth

LOBW#_BYPASS_HIBW = 0

0.7

1.1

1.4

MHz

8,9

Duty Cycle

Measured differentially, PLL Mode

45

50.1

55

%

1

Duty Cycle Distortion

Measured differentially, Bypass Mode

@100MHz

-2

0

2

%

1,10

PLL mode

34

50

ps

1,11

Additive Jitter in Bypass Mode

17

50

ps

1,11

Notes for preceding table:

Jitter, Cycle to cycle

Input to output skew is measured at the first output edge following the

corresponding input.