PTC04-DB-91209

PTC04 Daughter Board for MLX91209

PTC04-DB-91209

Datasheet

Rev. 1.0

Page 6 of 8

4/28/2011

1.3.3.

Force / Sense jumpers – J1

Force pin

Name

Sense pin

Name

1

VDD_DIE

2

VDD_SENSE_DIE

3

OUT_DIE1

4

OUT_SENSE_DIE1

5

OUT_DIE2

6

OUT_SENSE_DIE2

7

GND_DIE

8

GND_SENSE_DIE

1.4. Daughter board Connectors

The PTC04 main board has two connectors to the interface with the application. The PTC allows

adding a full PCB in between (Daughter Board). This daughter board can be mounted on the two

connectors. In some exceptional cases, a daughter board contains only a few wires from the Analogue

connector to the application connector. The pins on of the connectors are described below.

Meas_Line_P1

+36V_SUPPLY

ISENSE_PPS3

VOUT_PPS4

ANA.COMP2

ISENSE_PPS2

PE5

SDA

Rd

FC

ISENSE_PPS1

PE4

D1

VOUT_PPS3

A0

Meas_Line_P3

PE0

F8

A6

PE3

ANA.COMP0

D4

AGND

D6

PE7

Meas_Line_N3

D5

Meas_Line_P4

FA

Meas_Line_N2

SCL

VOUT_PPS1

D3

Wr

+5V_Digital_Supply

A4

FB

AGND

VOUT_PPS2

D2

D7

48 pin header

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

35

37

36

38

39

40

41

42

43

44

45

46

47

48

DIGITAL DB

CONNECTOR

Meas_Line_N4

Meas_Line_P2

ANALOG DB

CONNECTOR

PE1

40 Pin Header

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

A1

PE6

ANA.COMP3

Meas_Line_N1

FE

D0

+2.5V_REF_SUPPLY

DGND

ANA.COMP1

A7

FD

FF

A2

A5

A3

F9

PE2

Reset

ISENSE_PPS4

1.4.1.

Digital DB Connector (40 Pins)

Mainly, the digital connector is meant to expand the programmer to extra needs. Address lines

A0-A7 together with the Map Select Lines F8-FF allows to direct access an area of 2 K. Examples would

be adding a simple addressed I/O register by using the selection lines. If more complexity is needed, a full

FPGA can be mounted on the DB board

Pins

Names

Description

1 – 8

A0 – A7

Address lines

9 – 16

D0 – D7

Data Lines active during Rd or Wr signals

17

Rd

Read: A negative pulse will indicate a sampling of the data on the Data Bus

18

Wr

Write: A Negative pulse will indicate when data is available on the Data Bus

20

Reset

This signal goes low by powering the PTC or by pressing the reset button.

This line can be pulled low by application.

Check firmware documentation for resetting by software.

21-22

SCL / SDA

I

23-30

F8,F9,…,FF

CS lines when the address areas are accessed

31-38

Port E

The full Port E of the ATmega core is mounted to these pins. This allows us to use

advanced features like PWM, UARTS, Time Measurements, etc….