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IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

RapidWrite Mode Write Cycle

Unlike other vendors' Asynchronous Random Access Memories,

the IDT70T633/1 is capable of performing multiple back-to-back write

operations without having to pulse the R/W, CE, or BEn signals high

duringaddresstransitions. ThisRapidWriteModefunctionalityallowsthe

systemdesignertoachieveoptimumback-to-backwritecycleperformance

without the difficult task of generating narrow reset pulses every cycle,

simplifyingsystemdesignandreducingtimetomarket.

DuringthisnewRapidWriteMode,theendofthewritecycleisnow

definedbytheendingaddresstransition,insteadoftheR/WorCEorBEn

transition to the inactive state. R/W, CE, and BEn can be held active

throughout the address transition between write cycles.

whichtheAddressinputsmustbestable. Inputdatasetupandholdtimes

thisRapidWriteMode theI/OwillremainintheInputmodefortheduration

of the operations due to R/W being held low. All standard Write Cycle

applicable when switching between read and write operations. Also,

therearetwoadditionalconditionsontheAddressInputsthatmustalso

bemettoensurecorrectaddresscontrolled writes. Thesespecifications,

mustbemettousetheRapidWriteMode. Iftheseconditionsarenotmet

thereisthepotentialforinadvertentwriteoperationsatrandomintermediate

locationsasthedevicetransitionsbetweenthedesiredwriteaddresses.

5670 drw 08

ADDRESS

BEn

R/

W

(2)

(5)

(5)

(4)

NOTES:

R/W initiates the write sequence. The first transition HIGH of CE, BEn, and R/W terminates the write sequence.

4. The timing represented in this cycle can be repeated multiple times to execute sequential RapidWrite Mode writes.

5. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load

(Figure 1).