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KH560 Arkusz danych(PDF) 6 Page - Fairchild Semiconductor |
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KH560 Arkusz danych(HTML) 6 Page - Fairchild Semiconductor |
6 / 13 page DATA SHEET KH560 6 REV. 1A February 2001 SUMMARY DESIGN EQUATIONS AND DEFINITIONS KH560 Description of Operation Looking at the circuit of Figure 1 (the topology and resistor values used in setting the data sheet specifica- tions), the KH560 appears to bear a strong external resemblance to a classical op amp. As shown in the simplified block diagram of Figure 2, however, it differs in several key areas. Principally, the error signal is a current into the inverting input (current feedback) and the forward gain from this current to the output is relatively low, but very well controlled, current gain. The KH560 has been intentionally designed to have a low internal gain and a current mode output in order that an equivalent output impedance can be achieved without the series matching resistor more commonly required of low output impedance op amps. Many of the benefits of a high loop gain have, however, been retained through a very careful control of the KH560’s internal characteristics. The feedback and gain setting resistors determine both the output impedance and the gain. Rf predominately sets the output impedance (Ro), while Rg predominately determines the no load gain (Av). solving for the required Rf and Rg, given a desired Ro and Av, yields the design equations shown below. Conversely, given an Rf and Rg, the performance equations show that both Rf and Rg play a part in setting Ro and Av. Independent Ro and Av adjustment would be possible if the inverting input imped- ance (Ri) were 0 but, with Ri = 14Ω as shown in the specification listing, independent gain and output imped- ance setting is not directly possible. Figure 1: Test Circuit Design Equations Performance Equations Simplified Circuit Description Looking at the KH560’s simplified schematic in Figure 2, the amplifier’s operation may be described. Going from the non-inverting input at pin 8 to the inverting input at pin 18, transistors Q1 – Q4 act as an open loop unity gain buffer forcing the inverting node voltage to follow the non- inverting voltage input. Transistors Q3 and Q4 also act as a low impedance (14 Ω looking into pin 18) path for the feedback error current. This current, (ierr), flows through those transistors into a very well defined current mirror having a gain of 10 from this error current to the output. The current mirror outputs act as the amplifier output. The input stage bias currents are supply voltage inde- pendent. Since these set the bias level for the whole Rf – Feedback resistor from output to inverting input Rg – Gain setting resistor from inverting input to ground Cx – External compensation capacitor from output to pin 19 (in pF) Where: Ro – Desired equivalent output impedance Av – Non-inverting input to output voltage gain with no load G – Internal current gain from inverting input to output = 10 ±1% Ri – Internal inverting input impedance = 14Ω ±%5 Rs – Non-inverting input termination resistor RL – Load resistor AL – Voltage gain from non-inverting input to load resistor RG 1 R A R R RR A1 C 1 R 300 1 2 R 0.08 f ov i g f o v x o g =+ () − = − − = − − 6.8 µF .1 µF -VCC (-15) 410 Ω Rg 40 Ω 5,10,15, 20 Rf 21 KH560 + - 18 Rs 50 Ω 8 Vi (Pi) RL 50 Ω Vo (Po) Ro 4 19 +VCC (+15) .1 µF 6.8 µF + + Cx 23 10.5pF Resistor Values shown result in: Ro = 50 Ω Av = +10 (no-load gain) AL = +5 [14dB] (gain to 50 Ω load) RG 1 R A R R RR A1 f ov i g f o v =+ () − = − − R RR 1 R R G1 R R A1 R R G R R G1 R R o f i f g i g v f g i f i g = ++ ++ =+ − ++ Where: G ≡ forward current gain (=10) Ri ≡ inverting node input resistance (=14 Ω) Ro ≡ desired output impedance Av ≡ desired non- inverting voltage gain with no load |
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