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AK2401 Arkusz danych(PDF) 74 Page - Asahi Kasei Microsystems |
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AK2401 Arkusz danych(HTML) 74 Page - Asahi Kasei Microsystems |
74 / 103 page [AK2401] 017003093-E-00 2017/3 74 15.5. <0x0A~0x0B>CP Address D7 D6 D5 D4 D3 D2 D1 D0 R/W 0x0A X CPOF[1:0] CPFINE[4:0] R/W Initial value 0 0 0 0 0 0 0 0x0B X X X CPFAST[4:0] R/W Initial value 0 0 0 0 0 CPOF[1:0]: Phase Offset Adjustment by Frequency Phase Comparator Phase noise characteristics and spurious characteristics are affected by adding an offset to the phase when the frequency of an input signal that is input to the frequency phase comparator is locked. These characteristics could be improved by this setting with optimized conditions. Percentages in the table below are normalized. Normally, CPOF[1:0] bits must be set to “00”. CPOF Phase Offset [1] [0] 0 0 0% (default) 0 1 -11% 1 0 -20% 1 1 -27% CPFINE[4:0]: Charge Pump Current Setting for Normal Operation CPFAST[4:0]: Charge Pump Current Setting for First Lock Mode The charge pump current can be calculated by the equations below. Charge Pump Current [ μA] = I CP_MIN [μA] × (Setting Value + 1) ICP_MIN [μA] = 2025 / Resistor Connected to the [BIAS2] pin [kΩ] Charge Pump Current (Typ.) Unit: μA CPFAST[4:0] CPFINE[4:0] BIAS2 Pin Connected Resistance 33kΩ 27kΩ 22kΩ 0 61 75 92 1 123 150 184 2 184 225 276 3 246 300 368 ・・・ ・・・ n 2025 / BIAS2 Pin Resistance [k Ω]×(n+1) ・・・ ・・・ 28 1780 2175 2669 29 1841 2250 2761 30 1902 2325 2853 31 1964 2400 2946 |
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