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AK4376AECB Arkusz danych(PDF) 33 Page - Asahi Kasei Microsystems |
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AK4376AECB Arkusz danych(HTML) 33 Page - Asahi Kasei Microsystems |
33 / 68 page [AK4376A] 016014206-E-00 2016/11 - 33 - ■ PLL The PLL generates a PLLCLK which is used as the DAC operation clock DACMCLK. The output frequency should be set in the range from 101.6064 to 122.88MHz (Table 6 shows setting example of 48 kHz and 44.1 kHz base rates). Refer to Table 11 to Table 12 for frequency setting examples. Reference clock of PLL should be set in the range from 256 kHz to 3.072 MHz. Table 6. PLLCLK Setting Example 48 kHz base rate 44.1 kHz base rate 2560/fs 122.88 MHz 112.896 MHz 2304/fs 110.592 MHz 101.6064 MHz Reference clock = PLL Source / (PLD + 1) PLLCLK = Reference clock x (PLM + 1) DACMCLK = PLLCLK / (MDIV + 1) Figure 11. PLL Block Diagram ■ Input Clock Select Function The PLL has a function that selects the input clock. The clock source pin is selected by PLS[1:0] bits. Table 7. PLL Clock Select (x: Do not care) PLS[1:0] bits Clock Source 00 MCKI pin (default) 01 BCLK pin 1x X ’tal (XTI pin) 1. PLL Reference Clock Divider The PLL can set the dividing number of the reference clock in 16-bit. The input clock is used as PLL reference clock by dividing by (PLD+1). Table 8. PLL Reference Clock Divider PLD[15:0] bits Dividing Number 0000H 1 (default) 0001H to FFFFH 1 / (PLD + 1) Note 68. The reference clock divided by PLD should be set in the range from 256 kHz to 3.072 MHz. 1 ------------- (PLM+1) 1 ------------- (MDIV+1) 256 kHz to 3.072 MHz PLS[1:0] bits MCKI XTI BCLK 1 ------------- (PLD+1) PLL ANA Reference Feedback |
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