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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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AK4376AECB Arkusz danych(PDF) 60 Page - Asahi Kasei Microsystems |
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AK4376AECB Arkusz danych(HTML) 60 Page - Asahi Kasei Microsystems |
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60 / 68 page  [AK4376A] 016014206-E-00 2016/11 - 60 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0BH Lch Output Volume OVOLCN 0 0 OVL[4:0] 0CH Rch Output Volume 0 0 0 OVR[4:0] R/W R/W R R R/W Default 0 0 0 19H OVL[4:0]: DAC Lch Digital Volume Control; +3 dB to 12 dB & Mute, 0.5 dB step (Table 17) OVR[4:0]: DAC Rch Digital Volume Control; +3 dB to 12 dB & Mute, 0.5 dB step (Table 17) Default: “19H” (0 dB) OVOLCN: Digital Volume Control 0: Dependent (default) 1: Independent OVL[4:0] bits control digital volume of both L and R channels when OVOLCN bit = “0”. In this case, the value of OVL[4:0] bits will not be written to OVR[4:0] bits. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0DH HP Volume Control 0 0 0 0 HPG[3:0] R/W R R R R R/W Default 0 0 0 0 BH HPG[3:0]: HP-Amp Analog Volume Control; +6 dB to 20 dB, 2 dB step (Table 21) Default: BH (0 dB) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0EH PLL CLK Source Select 0 0 T2 0 0 0 PLS[1:0] R/W R R R/W R R R R/W Default 0 0 0 0 0 0 00 PLS[1:0]: PLL Clock Source Select (Table 7) Default: “00” (MCKI pin) T2: Write “0” into this bit. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0FH PLL Ref CLK Divider 1 PLD[15:8] 10H PLL Ref CLK Divider 2 PLD[7:0] R/W R/W Default 0000H PLD[15:0]: PLL Reference Clock Divider Setting (Table 8) Default: 0000H (Divided by 1) |
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