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IIS328DQ Arkusz danych(PDF) 27 Page - STMicroelectronics |
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IIS328DQ Arkusz danych(HTML) 27 Page - STMicroelectronics |
27 / 40 page DocID027250 Rev 3 27/40 IIS328DQ Register description 40 7.5 CTRL_REG4 (23h) Table 26. CTRL_REG3 description IHL Interrupt active-high/low. Default value: 0 (0: active high; 1: active low) PP_OD Push-pull/open-drain selection on interrupt pad. Default value 0 (0: push-pull; 1: open drain) LIR2 Latch interrupt request on the INT2_SRC register, with the INT2_SRC register cleared by reading INT2_SRC itself. Default value: 0 (0: interrupt request not latched; 1: interrupt request latched) I2_CFG1, I2_CFG0 Data signal on INT 2 pad control bits. Default value: 00 (see Table 27) LIR1 Latch interrupt request on the INT1_SRC register, with the INT1_SRC register cleared by reading the INT1_SRC register. Default value: 0 (0: interrupt request not latched; 1: interrupt request latched) I1_CFG1, I1_CFG0 Data signal on INT 1 pad control bits. Default value: 00 (see Table 27) Table 27. Data signal on INT 1 and INT 2 pad I1(2)_CFG1 I1(2)_CFG0 INT 1(2) Pad 0 0 Interrupt 1 (2) source 0 1 Interrupt 1 source OR interrupt 2 source 1 0 Data ready 1 1 Boot running Table 28. CTRL_REG4 register BDU BLE FS1 FS0 STsign 0 ST SIM Table 29. CTRL_REG4 description BDU Block data update. Default value: 0 (0: continuous update; 1: output registers not updated between reading MSb and LSb) BLE Big/little endian data selection. Default value 0 (0: data LSb @ lower address; 1: data MSb @ lower address) FS1, FS0 Full-scale selection. Default value: 00 (00: ±2 g; 01: ±4 g; 11: ±8 g) STsign Self-test sign. Default value: 00 (0: self-test plus; 1 self-test minus) ST Self-test enable. Default value: 0 (0: self-test disabled; 1: self-test enabled) SIM SPI serial interface mode selection. Default value: 0 (0: 4-wire interface; 1: 3-wire interface) |
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