Product Specification

PE4312

Page 5 of 13

Document No. DOC-81482-1 │ www.psemi.com

©2017 Peregrine Semiconductor Corp. All rights reserved.

Programming Options

Parallel/Serial Selection

Either a parallel or serial interface can be used to

control the PE4312. The P/S bit provides this

selection, with P/S = LOW selecting the parallel

interface and P/S = HIGH selecting the serial

interface.

Parallel Mode Interface

The parallel interface consists of six CMOS-

compatible control lines that select the desired

attenuation state, as shown in Table 5.

The parallel interface timing requirements are

defined by Figure 5 (Parallel Interface Timing

Diagram), Table 9 (Parallel Interface AC

Characteristics), and switching speed (Table 1).

For latched parallel programming the Latch Enable

(LE) should be held LOW while changing attenuation

state control values, then pulse LE HIGH to LOW

(per Figure 5) to latch the new attenuation state into

the device.

For direct parallel programming, the Latch Enable

(LE) line should be pulled HIGH. Changing

attenuation state control values will change device

state to new attenuation. Direct Mode is ideal for

manual control of the device (using hardwire,

switches, or jumpers).

P/S

C16

C8

C4

C2

C1

C0.5 Attenuation State

0

0

0

0

0

0

0

Reference Loss

0

0

0

0

0

0

1

0.5 dB

0

0

0

0

0

1

0

1 dB

0

0

0

0

1

0

0

2 dB

0

0

0

1

0

0

0

4 dB

0

0

1

0

0

0

0

8 dB

0

1

0

0

0

0

0

16 dB

0

1

1

1

1

1

1

31.5 dB

Table 5. Truth Table*

Note: * Not all 64 possible combinations of C0.5–C16 are shown in table.

Serial Interface

The serial interface is a 6-bit serial-in, parallel-out

shift register buffered by a transparent latch. It is

controlled by three CMOS-compatible signals: Data,

Clock, and Latch Enable (LE). The Data and Clock

inputs allow data to be serially entered into the shift

register, a process that is independent of the state of

the LE input.

The LE input controls the latch. When LE is HIGH,

the latch is transparent and the contents of the serial

shift register control the attenuator. When LE is

brought LOW, data in the shift register is latched.

The shift register should be loaded while LE is held

LOW to prevent the attenuator value from changing

as data is entered. The LE input should then be

toggled HIGH and brought LOW again, latching the

new data. The timing for this operation is defined by

Figure 5 (Serial Interface Timing Diagram) and

Table 8 (Serial Interface AC Characteristics).

Power-up Control Settings

The PE4312 always assumes a specifiable

attenuation setting on power-up. This feature exists

for both the Serial and Parallel modes of operation,

and allows a known attenuation state to be

established before an initial serial or parallel control

word is provided.

When the attenuator powers up in Serial mode

(P/S = 1), the six control bits are set to whatever

data is present on the six parallel data inputs (C0.5

to C16). This allows any one of the 64 attenuation

settings to be specified as the power-up state.

When the attenuator powers up in Parallel mode

(P/S = 0) with LE = 0, the control bits are

automatically set to one of four possible values.

These four values are selected by the two power-up

control bits, PUP1 and PUP2, as shown in Table 6

(Power-Up Truth Table, Parallel Mode).

P/S

LE

PUP2

PUP1

Attenuation State

0

0

0

0

Reference Loss

0

0

1

0

8 dB

0

0

0

1

16 dB

0

0

1

1

31.5 dB

0

1

X

X

Defined by C0.5-C16

Table 6. Parallel PUP Truth Table*

Note: * Power up with LE = 1 provides normal parallel operation with C0.5-C16,

and PUP1 and PUP2 are not active.